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ORCIDVLSI Design, Volume 2016
Volume 2016, 2016
- Weigong Zhang, Li Chao, Keni Qiu, Shaonan Zhang, Xianglong Chen:
A Novel Time Synchronization Method for Dynamic Reconfigurable Bus. 5752080:1-5752080:10 - Apangshu Das
, Sambhu Nath Pradhan:
Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. 3191286:1-3191286:14 - Vikas K. Saini, Shamim Akhter, Tanuj Chauhan:
Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits. 1260879:1-1260879:8 - Xingyuan Tong, Tiantian Sun:
Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics. 6029254:1-6029254:6 - Neeta Pandey, Kirti Gupta, Bharat Choudhary:
New Proposal for MCML Based Three-Input Logic Implementation. 8712768:1-8712768:10 - Satish S. Bhairannawar, K. B. Raja, K. R. Venugopal:
An Efficient Reconfigurable Architecture for Fingerprint Recognition. 9532762:1-9532762:22 - Arezoo Kamran, Zainalabedin Navabi:
Self-Healing Many-Core Architecture: Analysis and Evaluation. 9767139:1-9767139:17 - Hongmei Chen, Yong-Sheng Yin, Honghui Deng, Fujiang Lin:
A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs. 6475932:1-6475932:8 - Abhishek Jain, Richa Gupta:
Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors. 7283471:1-7283471:14 - Mamata Dalui, Biplab K. Sikdar:
A Cache System Design for CMPs with Built-In Coherence Verification. 8093614:1-8093614:16 - Lan Dai, Cheng-Ying Chen:
A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic. 6708253:1-6708253:7 - Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu:
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW. 8787919:1-8787919:12
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