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ORCIDAlexander Barkalov 0001
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- affiliation: University of Zielona Góra, Poland
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2020 – today
- 2024
[j16]Alexander Barkalov
, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz:
Hardware Reduction for FSMs With Extended State Codes. IEEE Access 12: 42369-42384 (2024)- [j15]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Reducing the number of LUTs for Mealy FSMs with state transformation. Int. J. Appl. Math. Comput. Sci. 34(1) (2024) - [j14]Larysa Titarenko, Vyacheslav Kharchenko, Vadym Puidenko, Artem Perepelitsyn, Alexander Barkalov:
Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores. Comput. 13(7): 166 (2024) - 2022
- [b5]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz, Elzbieta Kawecka:
Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs. Lecture Notes in Electrical Engineering 922, Springer 2022, ISBN 978-3-031-16026-4, pp. 1-286 - [j13]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek:
Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access 10: 36152-36165 (2022) - [j12]Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz:
Improving the LUT Count for Mealy FSMS with Transformation of Output Collections. Int. J. Appl. Math. Comput. Sci. 32(3): 479-494 (2022) - [j11]Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek:
Reducing LUT Count for Mealy FSMs With Transformation of States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1400-1411 (2022) - 2021
- [c32]Kazimierz Krzywicki, Grzegorz Andrzejewski, Wojciech Zajac, Tomasz Królikowski, Alexander Barkalov, Larysa Titarenko:
IPNES - Interpreted Petri Net for Embedded Systems. KES 2021: 2012-2021 - 2020
- [b4]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski:
Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design. Lecture Notes in Electrical Engineering 636, Springer 2020, ISBN 978-3-030-38294-0, pp. 1-241 - [j10]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Improving Characteristics of LUT-Based Moore FSMs. IEEE Access 8: 155306-155318 (2020) - [j9]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Improving characteristics of LUT-based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 30(4): 745-759 (2020)
2010 – 2019
- 2019
- [j8]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. J. Circuits Syst. Comput. 28(8): 1950131:1-1950131:21 (2019) - [c31]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Kazimierz Krzywicki, Wojciech Zajac:
Decreasing Number of LUTs for Moore FSMs. MIXDES 2019: 200-205 - [c30]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek:
Design of FPGA-Based Mealy FSMs with Counters. MOCAST 2019: 1-4 - [c29]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Designing FPGA-Based Mealy FSMs with Two Levels of Logic. MOCAST 2019: 1-4 - [c28]Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek:
Encoding of Microoperations in FPGA-Based Moore FSMs. MOCAST 2019: 1-4 - 2018
- [j7]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Hardware Reduction for Lut-Based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 28(3): 595-607 (2018) - [c27]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski:
Design of FPGA-based Mealy FSMs with Counters. MIXDES 2018: 136-139 - [c26]Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek:
Encoding of Terms in LUT-based Mealy FSMs. MIXDES 2018: 145-148 - [c25]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Twofold State Assignment for LUT-based Mealy FSMs. MIXDES 2018: 204-208 - [c24]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Design of CPLD-based mealy FSMs with counters. MOCAST 2018: 1-4 - [c23]Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Twofold state assignment for FPGA-based mealy FSMs. MOCAST 2018: 1-4 - 2017
- [j6]Malgorzata Kolopienczyk, Larysa Titarenko, Alexander Barkalov:
Design of EMB-Based Moore FSMs. J. Circuits Syst. Comput. 26(7): 1750125:1-1750125:23 (2017) - [c22]Kamil Mielcarek, Alexander Barkalov, Larisa Titarenko:
Designing Moore FSM with Transformation of State Codes. CISIM 2017: 557-568 - [c21]Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko:
Designing HFPGA-based Mealy FSMs with transformation of output functions. MIXDES 2017: 250-253 - [c20]Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski:
Designing HFPGA-based FSMs with counters. MIXDES 2017: 254-257 - [c19]Kazimierz Krzywicki, Alexander Barkalov, Grzegorz Andrzejewski, Larysa Titarenko, Malgorzata Kolopienczyk:
CloudBus protocol hardware multi-converter gateway for distributed embedded systems. MIXDES 2017: 549-552 - [c18]Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski:
Code sharing in CPLD-based Moore FSMs. MOCAST 2017: 1-4 - [c17]Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko:
Designing Moore FSM with extended class codes. MOCAST 2017: 1-4 - 2014
- [j5]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Hardware Reduction in CPLD-Based Moore FSM. J. Circuits Syst. Comput. 23(6) (2014) - [c16]Larysa Titarenko, Olena Hebda, Alexander Barkalov:
Design of Moore finite state machine with coding space stretching. HSI 2014: 238-242 - [c15]Malgorzata Kolopienczyk, Alexander Barkalov, Larysa Titarenko:
Hardware reduction for RAM-based Moore FSMs. HSI 2014: 255-260 - 2013
- [j4]Alexander Barkalov, Larysa Titarenko, Raisa Malcheva, Kyryll Soldatov:
Hardware Reduction in FPGA-Based Moore FSM. J. Circuits Syst. Comput. 22(3) (2013) - [c14]Alexander Barkalov, Roman Babakov, Larysa Titarenko:
Compositional microprogram control unit with operational automaton of transitions. EWDTS 2013: 1-4 - [c13]Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski:
Hardware reduction for compositional microprogram control unit dedicated for CPLD systems. EWDTS 2013: 1-6 - [c12]Larysa Titarenko, Olena Hebda, Alexander Barkalov:
Design of moore finite state machine with extended state codes. ITI 2013: 347-352 - [c11]Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski:
Design of FPGA-Based Moore FMSs with Counters. PDeS 2013: 171-174 - [c10]Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk:
EMB - Based Design of Mealy FSM. PDeS 2013: 215-220 - [c9]Alexander Barkalov, Slawomir Chmielewski, Larysa Titarenko:
Synthesis of Moore Finite State Machines Based on Pseudoequivalent States. PDeS 2013: 233-238 - [c8]Alexander Barkalov, Larysa Titarenko, Roman Babakov:
Compositional Microprogram Control Unit with Operational Automaton of Transitions. PDeS 2013: 239-244 - [c7]Larysa Titarenko, Olena Hebda, Alexander Barkalov:
Synthesis of PLA-Based Moore FSM with Unconventional Presentation of State Codes. PDeS 2013: 250-255 - 2011
- [b3]Vladimir Popovskij, Alexander Barkalov, Larysa Titarenko:
Control and Adaptation in Telecommunication Systems - Mathematical Foundations. Lecture Notes in Electrical Engineering 94, Springer 2011, ISBN 978-3-642-20613-9, pp. 1-172 [contents] - [j3]Remigiusz Wisniewski, Alexander Barkalov, Larysa Titarenko, Wolfgang A. Halang:
Design of microprogrammed controllers to be implemented in FPGAs. Int. J. Appl. Math. Comput. Sci. 21(2): 401-412 (2011) - [c6]Alexander Barkalov, Larysa Titarenko, Lukasz Smolinski:
Optimization of microprogram control unit with code sharing. EWDTS 2011: 55-59 - [c5]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Synthesis of control unit with refined state encoding for CPLD devices. EWDTS 2011: 60-65 - [c4]Alexander Barkalov, Larysa Titarenko, Olena Hebda:
Hardware reduction for matrix circuit of control Moore automaton. EWDTS 2011: 94-98 - 2010
- [j2]Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski:
Reduction in the number of LUT elements for control units with code sharing. Int. J. Appl. Math. Comput. Sci. 20(4): 751-761 (2010) - [c3]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Hardware reduction for FSM - Based control units using PAL technology. EWDTS 2010: 21-24 - [c2]Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski:
Microprogram control unit with code sharing and extended microinstruction format. EWDTS 2010: 73-76 - [c1]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. EWDTS 2010: 390-394
2000 – 2009
- 2009
- [b2]Alexander Barkalov, Larysa Titarenko:
Logic Synthesis for FSM-Based Control Units. Lecture Notes in Electrical Engineering 53, Springer 2009, ISBN 978-3-642-04308-6, pp. 1-229 [contents] - 2008
- [b1]Alexander Barkalov, Larysa Titarenko:
Logic Synthesis for Compositional Microprogram Control Units. Lecture Notes in Electrical Engineering 22, Springer 2008, ISBN 978-3-540-69283-6, pp. 1-267 - 2007
- [j1]Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM. Int. J. Appl. Math. Comput. Sci. 17(4): 565-575 (2007)
Coauthor Index
aka: Larisa Titarenko
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