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ORCIDAd J. van de Goor
Adrianus J. van de Goor
Person information
- affiliation: Delft University of Technology, Department of Electrical Engineering, The Netherlands
- affiliation (PhD 1970): Carnegie Mellon University, Pittsburgh, PA, USA
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Books and Theses
- 1989
[b1]Ad J. van de Goor:
Computer architecture and design. Electronic systems engineering series, Addison-Wesley 1989, ISBN 978-0-201-18241-5, pp. I-XVIII, 1-633
Journal Articles
- 2006
- [j35]Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor:
Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55(12): 1630-1639 (2006) - [j34]Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Sultan M. Al-Harbi:
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2989-2996 (2006) - 2004
- [j33]Ad J. van de Goor:
An Industrial Evaluation of DRAM Tests. IEEE Des. Test Comput. 21(5): 430-440 (2004) - [j32]Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor:
Memory Fault Modeling Trends: A Case Study. J. Electron. Test. 20(3): 245-255 (2004) - [j31]Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers:
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 737-757 (2004) - 2003
- [j30]Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers:
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electron. Test. 19(2): 195-205 (2003) - [j29]Zaid Al-Ars, Ad J. van de Goor:
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. IEEE Trans. Computers 52(3): 293-309 (2003) - [j28]Ad J. van de Goor, Issam B. S. Tlili:
A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories. IEEE Trans. Computers 52(10): 1320-1331 (2003) - [j27]Zaid Al-Ars, Ad J. van de Goor:
Test generation and optimization for DRAM cell defects using electrical simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1371-1384 (2003) - 2002
- [j26]Said Hamdioui, Ad J. van de Goor:
Efficient Tests for Realistic Faults in Dual-Port SRAMs. IEEE Trans. Computers 51(5): 460-473 (2002) - [j25]Said Hamdioui, Ad J. van de Goor:
Thorough testing of any multiport memory with linear tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 217-231 (2002) - 2000
- [j24]Said Hamdioui, Ad J. van de Goor:
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. J. Electron. Test. 16(5): 487-498 (2000) - 1998
- [j23]R. D. L. Stout, Ad J. van de Goor, R. E. Wolff:
Automatic fault localization at chip level. Microprocess. Microsystems 22(1): 13-22 (1998) - 1994
- [j22]Ad J. van de Goor, Yervant Zorian:
Effective march algorithms for testing single-order addressed memories. J. Electron. Test. 5(4): 337-345 (1994) - [j21]Fabian Klass, Michael J. Flynn, Ad J. van de Goor:
Fast multiplication in VLSI using wave pipelining techniques. J. VLSI Signal Process. 7(3): 233-248 (1994) - 1993
- [j20]Ad J. van de Goor:
Using March Tests to Test SRAMs. IEEE Des. Test Comput. 10(1): 8-14 (1993) - 1991
- [j19]Ad J. van de Goor, J. A. M. van Tetering:
A low-cost tester for boundary scan. Microprocess. Microsystems 15(2): 82-90 (1991) - 1990
- [j18]Ad J. van de Goor, C. A. Verruijt:
An Overview of Deterministic Functional RAM Chip Testing. ACM Comput. Surv. 22(1): 5-33 (1990) - [j17]P. P. Meiler, Ad J. van de Goor:
The Delft test system. Microprocessing and Microprogramming 29(1): 27-41 (1990) - [j16]Ad J. van de Goor, O. Jansen:
Self test for the Intel 8085. Microprocessing and Microprogramming 29(3): 165-175 (1990) - [j15]P. B. Franken, Ad J. van de Goor:
Special architecture for high-performance scan conversion. Microprocessing and Microprogramming 30(1-5): 431-438 (1990) - 1989
- [j14]A. M. Levy, Adrianus J. van de Goor, Jan van Katwijk:
Distributed system design using Ada as a tool for prototyping. Microprocessing and Microprogramming 27(1-5): 221-230 (1989) - [j13]M. A. van Peursem, P. Knoppers, Ad J. van de Goor:
TLS: a system for building and controlling transputer networks. Microprocessing and Microprogramming 27(1-5): 739-746 (1989) - 1988
- [j12]P. Knoppers, Ad J. van de Goor, O. M. Gunhildsbu, P. Stravers:
Transputer network with flexible topology. Microprocess. Microprogramming 24(1-5): 275-279 (1988) - [j11]Ad J. van de Goor, G. J. Nanninga:
Speech synthesis system with unlimited vocabulary for the Dutch language. Microprocess. Microprogramming 24(1-5): 325-333 (1988) - [j10]Reinder J. Bril, Ad J. van de Goor:
Software transparent cache consistency scheme for a VMEbus-based system. Microprocess. Microsystems 12(9): 513-518 (1988) - [j9]Petra De Jong, Ad J. van de Goor:
Test Pattern Generation for API Faults in RAM. IEEE Trans. Computers 37(11): 1426-1428 (1988) - 1987
- [j8]Ad J. van de Goor, A. C. van Wijngaarden:
Multiprocessing memory subsystem. Microprocess. Microsystems 11(7): 357-364 (1987) - [j7]T. A. Peelen, Ad J. van de Goor:
Using the page mode of dynamic RAMs to obtain a pseudo cache. Microprocess. Microsystems 11(9): 469-473 (1987) - [j6]G. J. Dekker, Ad J. van de Goor:
Amore Address Mapping with Overlapped Rotating Entries. IEEE Micro 7(3): 22-34 (1987) - 1986
- [j5]M. D. Janssens, J. K. Annot, Ad J. van de Goor:
Adapting UNIX for a Multiprocessor Environment. Commun. ACM 29(9): 895-901 (1986) - [j4]J. K. Annot, M. D. Janssens, Ad J. van de Goor:
Comments on Morris's Starvation-Free Solution to the Mutual Exclusion Problem. Inf. Process. Lett. 23(2): 91-97 (1986) - 1984
- [j3]Ad J. van de Goor:
Effects of technical developments on system security. Comput. Secur. 3(4): 314-322 (1984) - 1969
- [j2]Ad J. van de Goor, C. Gordon Bell, Donald A. Witcraft:
Design and Behavior of TSS/8: a PDP-8 Based Time-Sharing System. IEEE Trans. Computers 18(11): 1038-1043 (1969) - [j1]Ad J. van de Goor, C. Gordon Bell:
A Control Unit for a DEC PDP-8 Computer and a Burroughs Disk. IEEE Trans. Computers 18(11): 1044-1048 (1969)
Conference and Workshop Papers
- 2011
- [c95]Ad J. van de Goor, Said Hamdioui, Halil Kukner:
Generic, orthogonal and low-cost March Element based memory BIST. ITC 2011: 1-10 - 2010
- [c94]Ad J. van de Goor, Georgi Gaydadjiev
, Said Hamdioui:
Memory testing with a RISC microcontroller. DATE 2010: 214-219 - [c93]Said Hamdioui, Ad J. van de Goor:
Advanced embedded memory testing: Reducing the defect per million level at lower test cost. DDECS 2010: 7 - [c92]Ad J. van de Goor, Said Hamdioui, Georgi Gaydadjiev:
Using a CISC microcontroller to test embedded memories. DDECS 2010: 261-266 - [c91]Ad J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev:
Low-cost, customized and flexible SRAM MBIST engine. DDECS 2010: 382-387 - [c90]Ad J. van de Goor, Said Hamdioui:
MBIST architecture framework based on orthogonal constructs. IDT 2010: 128-133 - 2009
- [c89]Ad J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars:
New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. Asian Test Symposium 2009: 391-396 - 2008
- [c88]Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georg Mueller:
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. ITC 2008: 1-10 - 2006
- [c87]Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor:
Space of DRAM fault models and corresponding testing. DATE 2006: 1252-1257 - [c86]Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath:
DRAM-Specific Space of Memory Tests. ITC 2006: 1-10 - 2005
- [c85]Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van de Goor:
Framework for Fault Analysis and Test Generation in DRAMs. DATE 2005: 1020-1021 - [c84]Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Rob Wadsworth:
Impact of stresses on the fault coverage of memory tests. MTDT 2005: 103-108 - 2004
- [c83]Zaid Al-Ars, Ad J. van de Goor:
Soft Faults and the Importance of Stresses in Memory Testing. DATE 2004: 1084-1091 - [c82]Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars:
Tests for address decoder delay faults in RAMs due to inter-gate opens. ETS 2004: 146-151 - [c81]Ad J. van de Goor, Said Hamdioui, Rob Wadsworth:
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. ITC 2004: 114-123 - [c80]Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars:
The Effectiveness of the Scan Test and Its New Variants. MTDT 2004: 26-31 - [c79]Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor:
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT 2004: 32-37 - [c78]Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor:
The State-of-Art and Future Trends in Testing Embedded Memories. MTDT 2004: 54-59 - [c77]Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor:
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS 2004: 117-122 - 2003
- [c76]Zaid Al-Ars, Ad J. van de Goor:
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. Asian Test Symposium 2003: 24-27 - [c75]Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Mike Rodgers:
March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium 2003: 372-377 - [c74]Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter:
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. DATE 2003: 10484-10489 - [c73]Ivo Schanstra, Ad J. van de Goor:
Consequences of RAM Bitline Twisting for Test Coverage. DATE 2003: 11176-11177 - [c72]M. J. Geuzebroek, Ad J. van de Goor:
TPI for improving PR fault coverage of Boolean and three-state circuits. ETW 2003: 3-8 - [c71]Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor:
Importance of dynamic faults for new SRAM technologies. ETW 2003: 29-34 - [c70]Zaid Al-Ars, Ad J. van de Goor:
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. MTDT 2003: 27-32 - [c69]Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor:
A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT 2003: 33- - [c68]Said Hamdioui, Ad J. van de Goor, Mike Rodgers:
Detecting Intra-Word Faults in Word-Oriented Memories. VTS 2003: 241-247 - 2002
- [c67]Zaid Al-Ars, Ad J. van de Goor:
DRAM Specific Approximation of the Faulty Behavior of Cell Defects. Asian Test Symposium 2002: 98-103 - [c66]Zaid Al-Ars, Ad J. van de Goor:
Modeling Techniques and Tests for Partial Faults in Memory Devices. DATE 2002: 89-93 - [c65]Ad J. van de Goor, Magdy S. Abadir, Alan Carlin:
Minimal Test for Coupling Faults in Word-Oriented Memories. DATE 2002: 944-948 - [c64]Ad J. van de Goor, Ivo Schanstra:
Address and Data Scrambling: Causes and Impact on Memory Tests. DELTA 2002: 128-136 - [c63]M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor:
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. ITC 2002: 138-147 - [c62]Said Hamdioui, Ad J. van de Goor, Mike Rodgers:
March SS: A Test for All Static Simple RAM Faults. MTDT 2002: 95-100 - [c61]Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor:
Testing Static and Dynamic Faults in Random Access Memories. VTS 2002: 395-400 - [c60]Zaid Al-Ars, Ad J. van de Goor:
Approximating Infinite Dynamic Behavior for DRAM Cell Defects. VTS 2002: 401-406 - 2001
- [c59]Matthias Klaus, Ad J. van de Goor:
Tests for Resistive and Capacitive Defects in Address Decoders. Asian Test Symposium 2001: 31-36 - [c58]Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers:
Detecting Unique Faults in Multi-port SRAMs. Asian Test Symposium 2001: 37-42 - [c57]Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter:
A Memory Specific Notation for Fault Modeling. Asian Test Symposium 2001: 43- - [c56]Serge N. Demidenko, Ad J. van de Goor, S. Henderson, P. Knoppers:
Simulation and Development of Short Transparent Tests for RAM. Asian Test Symposium 2001: 164- - [c55]Zaid Al-Ars, Ad J. van de Goor:
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. DATE 2001: 496-503 - [c54]Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter:
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. ITC 2001: 783-792 - [c53]Zaid Al-Ars, Ad J. van de Goor:
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. MTDT 2001: 59-64 - [c52]Said Hamdioui, Ad J. van de Goor, David Eastwick, Mike Rodgers:
Realistic Fault Models and Test Procedures for Multi-Port SRAMs. MTDT 2001: 65-72 - 2000
- [c51]Said Hamdioui, Ad J. van de Goor:
An experimental analysis of spot defects in SRAMs: realistic fault models and tests. Asian Test Symposium 2000: 131-138 - [c50]Zaid Al-Ars, Ad J. van de Goor:
Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. Asian Test Symposium 2000: 282-289 - [c49]M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor:
Test point insertion for compact test sets. ITC 2000: 292-301 - [c48]Ad J. van de Goor, A. Paalvast:
Industrial evaluation of DRAM SIMM tests. ITC 2000: 426-435 - [c47]Said Hamdioui, Ad J. van de Goor, Mike Rodgers, David Eastwick:
March Tests for Realistic Faults in Two-Port Memories. MTDT 2000: 73-78 - [c46]Ad J. van de Goor, Zaid Al-Ars:
Functional Memory Faults: A Formal Notation and a Taxonomy. VTS 2000: 281-290 - 1999
- [c45]Ad J. van de Goor, J. E. Simonse:
Defining SRAM Resistive Defects and Their Simulation Stimuli. Asian Test Symposium 1999: 33-40 - [c44]Said Hamdioui, Ad J. van de Goor:
March Tests for Word-Oriented Two-Port Memories. Asian Test Symposium 1999: 53- - [c43]M. H. Konijnenburg, Hans van der Linden, Ad J. van de Goor:
Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. Asian Test Symposium 1999: 185-191 - [c42]Ad J. van de Goor, J. de Neef:
Industrial Evaluation of DRAM Tests. DATE 1999: 623-630 - [c41]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Illegal State Space Identification for Sequential Circuit Test Generation. DATE 1999: 741-746 - [c40]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Testability of the Philips 80C51 micro-controller. ITC 1999: 820-829 - [c39]Ad J. van de Goor, Ivo Schanstra:
Industrial evaluation of stress combinations for march tests applied to SRAMs. ITC 1999: 983-992 - [c38]Said Hamdioui, Ad J. van de Goor:
Port interference faults in two-port memories. ITC 1999: 1001-1010 - [c37]Daniel P. Van der Velde, Ad J. van de Goor:
Designing a Memory Module Tester. MTDT 1999: 91- - 1998
- [c36]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. Asian Test Symposium 1998: 212- - [c35]Said Hamdioui, Ad J. van de Goor:
Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. Asian Test Symposium 1998: 340-347 - [c34]Ad J. van de Goor:
Answers to the Key Issues. Asian Test Symposium 1998: 520 - [c33]Ad J. van de Goor, Issam B. S. Tlili:
March Tests for Word-Oriented Memories. DATE 1998: 501-508 - [c32]Said Hamdioui, Ad J. van de Goor:
Consequences of port restrictions on testing two-port memories. ITC 1998: 63-72 - [c31]Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Wijnen:
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories. ITC 1998: 872-881 - [c30]Ad J. van de Goor, Said Hamdioui:
Fault Models and Tests for Two-Port Memories. VTS 1998: 401-410 - 1997
- [c29]Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk:
March LA: a test for linked memory faults. ED&TC 1997: 627 - [c28]Ad J. van de Goor, Mike Lin:
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers. ITC 1997: 226-235 - [c27]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Sequential Test Generation with Advanced Illegal State Search. ITC 1997: 733-742 - [c26]Ad J. van de Goor, Issam B. S. Tlili:
Disturb Neighborhood Pattern Sensitive Fault. VTS 1997: 37-47 - 1996
- [c25]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. Asian Test Symposium 1996: 29-33 - [c24]Ad J. van de Goor, Georgi Gaydadjiev:
Realistic Linked Memory Cell Array Faults. Asian Test Symposium 1996: 183-188 - [c23]Ad J. van de Goor, Aad Offerman, Ivo Schanstra:
Towards a Uniform Notation for Memory Tests. ED&TC 1996: 420-427 - [c22]V. G. Mikitjuk, V. N. Yarmolik, Ad J. van de Goor:
RAM Testing Algorithm for Detection Linked Coupling Faults. ED&TC 1996: 435-441 - [c21]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Accelerated Compact Test Set Generation for Three-State Circuits. ITC 1996: 29-38 - [c20]Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik:
March LR: a test for realistic linked faults. VTS 1996: 272-280 - 1995
- [c19]Mark G. Karpovsky, Ad J. van de Goor, V. N. Yarmolik:
Pseudo-exhaustive word-oriented DRAM testing. ED&TC 1995: 126-132 - [c18]Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Functional test for shifting-type FIFOs. ED&TC 1995: 133-138 - [c17]Jos van Sas, Erik Huyskens, Hans Naert, Fred Schell, Ad J. van de Goor:
Coping with Re-usability Using Sequential ATPG: A Practical Case Study. ITC 1995: 252-261 - [c16]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Compact test sets for industrial circuits. VTS 1995: 358-366 - 1994
- [c15]Ad J. van de Goor, Yervant Zorian, Ivo Schanstra:
Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC 1994: 666 - [c14]Fabian Klass, Michael J. Flynn, Ad J. van de Goor:
A 16x16-bit Static CMOS Wave-Pipelined Multiplier. ISCAS 1994: 143-146 - [c13]Yervant Zorian, Ad J. van de Goor, Ivo Schanstra:
An Effective BIST Scheme for Ring-Address Type FIFOs. ITC 1994: 378-387 - [c12]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. ITC 1994: 604-613 - [c11]Ad J. van de Goor, B. Smit:
Generating March Tests Automatically. ITC 1994: 870-878 - [c10]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Test generation and three-state elements, buses, and bidirectionals. VTS 1994: 114-121 - [c9]Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Fault models and tests for Ring Address Type FIFOs. VTS 1994: 300-305 - [c8]Ad J. van de Goor, B. Smit:
Automating the verification of memory tests. VTS 1994: 312-318 - 1993
- [c7]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Test Pattern Generation with Restrictors. ITC 1993: 598-605 - 1992
- [c6]Ad J. van de Goor, Th. J. W. Verhallen:
Functional Testing of Current Microprocessors (applied to the Intel i860TM). ITC 1992: 684-695 - 1991
- [c5]Gert-Jan Tromp, Ad J. van de Goor:
Logic Synthesis of 100-percent Testable Logic Networks. ICCD 1991: 428-431 - [c4]Vlad. Hert, Ad J. van de Goor:
Truth Table Verification for one-Dimensional CMOS ILA's. Fault-Tolerant Computing Systems 1991: 205-216 - [c3]Ad J. van de Goor, P. C. M. van der Arend, Gert-Jan Tromp:
Locating Bridging Faults in Memory Arrays. ITC 1991: 685-694 - 1989
- [c2]Ad J. van de Goor, Henk Corporaal:
DOAS: an object oriented architecture supporting secure languages. MICRO 1989: 127-134 - 1988
- [c1]Ad J. van de Goor, A. Moolenaar:
UNIX I/O in a Multiprocessor System. USENIX Winter 1988: 251-258
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