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2000 – 2009
- 2002
[c12]M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor:
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. ITC 2002: 138-147- 2000
- [c11]M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor:
Test point insertion for compact test sets. ITC 2000: 292-301
1990 – 1999
- 1999
- [c10]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Illegal State Space Identification for Sequential Circuit Test Generation. DATE 1999: 741-746 - [c9]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Testability of the Philips 80C51 micro-controller. ITC 1999: 820-829 - 1998
- [c8]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. Asian Test Symposium 1998: 212- - 1997
- [c7]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Sequential Test Generation with Advanced Illegal State Search. ITC 1997: 733-742 - 1996
- [c6]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. Asian Test Symposium 1996: 29-33 - [c5]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Accelerated Compact Test Set Generation for Three-State Circuits. ITC 1996: 29-38 - 1995
- [c4]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Compact test sets for industrial circuits. VTS 1995: 358-366 - 1994
- [c3]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O. ITC 1994: 604-613 - [c2]J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Test generation and three-state elements, buses, and bidirectionals. VTS 1994: 114-121 - 1993
- [c1]M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor:
Test Pattern Generation with Restrictors. ITC 1993: 598-605
Coauthor Index
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