- 2016
- Amro Awad, Ganesh Balakrishnan, Yipeng Wang, Yan Solihin:
Accurate Cloning of the Memory Access Behavior. IPSJ Trans. Syst. LSI Des. Methodol. 9: 49-60 (2016) - Wing-Kai Chow, Evangeline F. Y. Young:
Placement: From Wirelength to Detailed Routability. IPSJ Trans. Syst. LSI Des. Methodol. 9: 2-12 (2016) - Ri Cui, Kazuteru Namba:
A Calibration Technique for DVMC with Delay Time Controllable Inverter. IPSJ Trans. Syst. LSI Des. Methodol. 9: 30-36 (2016) - Atsushi Hashimoto, Nagisa Ishiura:
Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs. IPSJ Trans. Syst. LSI Des. Methodol. 9: 21-29 (2016) - Yoshinobu Higami, Senling Wang
, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. 9: 13-20 (2016) - Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus. IPSJ Trans. Syst. LSI Des. Methodol. 9: 37-48 (2016) - Nana Sutisna, Reina Hongyo, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi:
Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System. IPSJ Trans. Syst. LSI Des. Methodol. 9: 61-71 (2016) - Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 9: 1 (2016) - Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ Trans. Syst. LSI Des. Methodol. 9: 79-83 (2016) - Michitarou Yabuuchi, Kazutoshi Kobayashi:
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. IPSJ Trans. Syst. LSI Des. Methodol. 9: 72-78 (2016) - 2015
- Matthias Jung, Christian Weis, Norbert Wehn:
DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework. IPSJ Trans. Syst. LSI Des. Methodol. 8: 63-74 (2015) - Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8: 116-122 (2015) - Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro:
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. IPSJ Trans. Syst. LSI Des. Methodol. 8: 95-99 (2015) - Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi:
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 8: 100-104 (2015) - Yusaku Hirai, Shinya Yano, Toshimasa Matsuoka:
A Delta-Sigma ADC with Stochastic Quantization. IPSJ Trans. Syst. LSI Des. Methodol. 8: 123-130 (2015) - Arif Ullah Khan, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model. IPSJ Trans. Syst. LSI Des. Methodol. 8: 38-50 (2015) - Tulika Mitra:
Heterogeneous Multi-core Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 8: 51-62 (2015) - Takaaki Miyajima, David B. Thomas, Hideharu Amano:
Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. IPSJ Trans. Syst. LSI Des. Methodol. 8: 105-115 (2015) - Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8: 131-135 (2015) - Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai:
An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. IPSJ Trans. Syst. LSI Des. Methodol. 8: 26-37 (2015) - Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 8: 1 (2015) - Lian Zeng, Xin Jiang, Takahiro Watanabe:
A Performance Enhanced Dual-switch Network-on-chip Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 8: 85-94 (2015) - Zhiru Zhang, Deming Chen, Steve Dai, Keith A. Campbell:
High-level Synthesis for Low-power Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 12-25 (2015) - Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 75-84 (2015) - Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. IPSJ Trans. Syst. LSI Des. Methodol. 8: 2-11 (2015) - 2014
- Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 74-80 (2014) - Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye:
Test and Design-for-Testability Solutions for 3D Integrated Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 7: 56-73 (2014) - Yuta Hagio, Masao Yanagisawa, Nozomu Togawa:
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 7: 81-90 (2014) - Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 37-45 (2014) - Tsung-Yi Ho:
Design Automation for Digital Microfluidic Biochips. IPSJ Trans. Syst. LSI Des. Methodol. 7: 16-26 (2014)
