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ORCIDQian Zhao 0001
Person information
- affiliation: Kyushu Institute of Technology, Iizuka-shi, Japan
- affiliation: Kumamoto University, Graduate School of Science and Technology, Kurokami, Japan
Other persons with the same name
- Qian Zhao — disambiguation page
- Qian Zhao 0002
![[0000-0001-9956-0064]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-9956-0064")
— Xi'an Jiaotong University, School of Mathematics and Statistics, China - Qian Zhao 0003 — Children's National Medical Center, Sheikh Zayed Institute for Pediatric Surgical Innovation, Washington DC, USA
- Qian Zhao 0004 — Tianjin University, College of Management and Economics, China
- Qian Zhao 0005 — Chinese University of Hong Kong
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2020 – today
- 2023
[j14]Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida:
An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 560-574 (2023)- 2022
- [j13]Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida:
Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 448-458 (2022) - [c25]Hui Meng, Qian Zhao, Takaichi Yoshida:
A Study of Reconfigurable Switch Architecture for Chiplets Interconnection. CANDARW 2022: 69-75 - 2021
- [c24]Longzhen Yu, Qian Zhao, Zhixian Wang:
Attention Mechanism Driven YOLOv3 on FPGA Acceleration for Efficient Vision Based Defect Inspection. CSAE 2021: 90:1-90:5 - [c23]Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga:
Automation of Domain-specific FPGA-IP Generation and Test. HEART 2021: 4:1-4:6 - 2020
- [c22]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida:
Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. CANDAR 2020: 235-241 - [c21]Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida:
A Microcode-based Control Unit for Deep Learning Processors. IPDPS Workshops 2020: 139-142
2010 – 2019
- 2019
- [j12]Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida:
A SLM-based overlay architecture for fine-grained virtual FPGA. IEICE Electron. Express 16(24): 20190610 (2019) - [c20]Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida:
A Resource Reduced Application-Specific FPGA Switch. ARC 2019: 58-67 - [c19]Qian Zhao, Takaichi Yoshida:
A Platform-as-a-Service System for FPGA Education and Development. CompEd 2019: 243 - [c18]Ryota Watanabe, Saika Ura, Qian Zhao, Takaichi Yoshida:
Implementation of FPGA Building Platform as a Cloud Service. HEART 2019: 6:1-6:6 - [c17]Ryota Watanabe, Yuki Katsuda, Qian Zhao, Takaichi Yoshida:
A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network. CANDAR Workshops 2019: 115-120 - [c16]Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama:
A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC 2019: 74-80 - 2018
- [j11]Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi:
Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. 101-D(2): 278-287 (2018) - [j10]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. 101-D(2): 335-343 (2018) - [c15]Mahdillah Mahdillah, Shinya Nakayama, Qian Zhao, Takaichi Yoshida:
An Adaptable Scheduling for Self-Reconfigurable Objects. CANDAR Workshops 2018: 331-336 - 2017
- [j9]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10: 63-70 (2017) - [c14]Qian Zhao, Masahiro Iida, Toshinori Sueyoshi:
A Study of FPGA Virtualization and Accelerator Scheduling. ETCD@ASPLOS 2017: 3:1-3:4 - [c13]Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT 2017: 267-270 - 2016
- [j8]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44(4): 86-91 (2016) - [c12]Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE: An open-source platform for FPGA accelerators. FPT 2016: 205-208 - 2015
- [j7]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. 98-D(2): 252-261 (2015) - [j6]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10(3): 425-431 (2015) - [j5]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8: 116-122 (2015) - [c11]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Simple wafer stacking 3D-FPGA architecture. ICICDT 2015: 1-4 - [c10]Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC 2015: 110-115 - 2014
- [c9]Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL 2014: 1-6 - [c8]Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi:
A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT 2014: 306-309 - 2013
- [j4]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. 96-D(8): 1602-1612 (2013) - [c7]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA 2013: 271 - [c6]Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL 2013: 1-7 - [c5]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An automatic FPGA design and implementation framework. FPL 2013: 1-4 - [c4]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC 2013: 1-7 - [c3]Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC 2013: 192-197 - 2012
- [j3]Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi:
COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. 95-D(2): 294-302 (2012) - 2011
- [j2]Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. 3(3): 89-92 (2011) - [c2]Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A novel reconfigurable logic device base on 3D stack technology. 3DIC 2011: 1-4 - 2010
- [j1]Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4(1): 5:1-5:24 (2010) - [c1]Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A robust reconfigurable logic device based on less configuration memory logic cell. FPT 2010: 162-169
Coauthor Index
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