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2010 – 2019
- 2018
[c10]Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara
, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka:
Understanding Fake Faces. ECCV Workshops (3) 2018: 566-576- [i1]Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka:
Understanding Fake Faces. CoRR abs/1809.08391 (2018) - 2017
- [j5]Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. 100-D(4): 633-644 (2017) - 2013
- [j4]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. 96-D(8): 1602-1612 (2013) - [c9]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA 2013: 271 - [c8]Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL 2013: 1-7 - 2012
- [j3]Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. 95-D(2): 303-313 (2012) - [c7]Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault detection and avoidance of FPGA in various granularities. FPL 2012: 539-542 - [c6]Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel physical defects recovery technique for FPGA-IP cores. ReConFig 2012: 1-7 - [c5]Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC 2012: 225-230 - 2011
- [j2]Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi:
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. 94-C(4): 548-556 (2011) - [c4]Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Efficient Test Technique. FPL 2011: 291-294 - [c3]Masahiro Toba, Yuji Hayashi, Koji Murai, Kazuki Inoue:
Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition. SoSE 2011: 72-76 - [c2]Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi:
An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109 - 2010
- [j1]Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4(1): 5:1-5:24 (2010)
2000 – 2009
- 2009
- [c1]Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC 2009: 97-109
Coauthor Index
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