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2020 – today
- 2021
[c24]Wakako Nakano, Yukino Shinohara, Nagisa Ishiura:
Full Hardware Implementation of FreeRTOS-Based Real-Time Systems. TENCON 2021: 435-440
2010 – 2019
- 2018
- [c23]Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara:
Synthesis of Full Hardware Implementation of RTOS-Based Systems. RSP 2018: 1-7 - [c22]Shogo Takakura, Mitsuyoshi Iwatsuji, Nagisa Ishiura:
Extending equivalence transformation based program generator for random testing of C compilers. A-TEST@ESEC/SIGSOFT FSE 2018: 9-15 - [c21]Kota Kitaura, Nagisa Ishiura:
Random testing of compilers' performance based on mixed static and dynamic code comparison. A-TEST@ESEC/SIGSOFT FSE 2018: 38-44 - 2017
- [j12]Yusuke Hibino, Hirofumi Ikeo, Nagisa Ishiura:
CF3: Test Suite for Arithmetic Optimization of C Compilers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1511-1512 (2017) - [c20]Kagumi Azuma, Nagisa Ishiura, Nobuaki Yoshida, Hiroyuki Kanbara:
Distributed memory architecture for high-level synthesis of embedded controllers from Erlang. Erlang Workshop 2017: 13-19 - [c19]Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama:
Binary synthesis implementing external interrupt handler as independent module. RSP 2017: 92-98 - [c18]Miho Shimizu, Nagisa Ishiura, Sayuri Ota, Wakako Nakano:
Speculative execution in distributed controllers for high-level synthesis. RSP 2017: 99-104 - 2016
- [j11]Atsushi Hashimoto, Nagisa Ishiura:
Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs. IPSJ Trans. Syst. LSI Des. Methodol. 9: 21-29 (2016) - [c17]Kazuhiro Nakamura, Nagisa Ishiura:
Random testing of C compilers based on test program generation by equivalence transformation. APCCAS 2016: 676-679 - [c16]Daisuke Fujiwara, Nagisa Ishiura, Ryo Sakai, Ryo Aoki, Takashi Ogawara:
Reverse Engineering from Mainframe Assembly to C Codes in Legacy Migration. IIAI-AAI 2016: 1058-1063 - 2014
- [j10]Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura:
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. Inf. Media Technol. 9(4): 456-465 (2014) - [j9]Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura:
Reinforcing Random Testing of Arithmetic Optimization of C Compilers by Scaling up Size and Number of Expressions. IPSJ Trans. Syst. LSI Des. Methodol. 7: 91-100 (2014) - 2010
- [j8]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). Inf. Media Technol. 5(4): 1064-1081 (2010) - [j7]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). IPSJ Trans. Syst. LSI Des. Methodol. 3: 161-178 (2010) - [j6]Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai:
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. IPSJ Trans. Syst. LSI Des. Methodol. 3: 207-221 (2010)
2000 – 2009
- 2008
- [j5]Nagisa Ishiura:
Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3413-3414 (2008) - [j4]Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama:
High-Level Synthesis of Software Function Calls. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3556-3558 (2008) - 2002
- [c15]Nagisa Ishiura, Tatsuo Watanabe:
Datapath oriented codesign method of application specific DSPs using retargetable compiler. APCCAS (1) 2002: 55-58 - 2000
- [c14]Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe:
Thread partitioning method for hardware compiler bach. ASP-DAC 2000: 303-308
1990 – 1999
- 1998
- [c13]Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe:
Binding and Scheduling Algorithms for Highly Retargetable Compilation. ASP-DAC 1998: 93-98 - 1995
- [c12]Akihisa Yamada, Satoru Nakamura, Nagisa Ishiura, Isao Shirakawa, Takashi Kambe:
Optimal Scheduling for Conditional Recource Sharing. ISCAS 1995: 2297-2300 - 1994
- [j3]Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima:
Fault simulation for multiple faults by Boolean function manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 531-535 (1994) - 1992
- [c11]Nagisa Ishiura, Shuzo Yajima:
Linear time fault simulation algorithm using a content addressable memory. EURO-DAC 1992: 442-445 - 1991
- [c10]Hiroyuki Ochi, Nagisa Ishiura, Shuzo Yajima:
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing. DAC 1991: 413-416 - [c9]Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima:
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. DAC 1991: 650-655 - [c8]Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima:
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. ICCAD 1991: 472-475 - [c7]Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima:
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. ICCAD 1991: 550-553 - 1990
- [j2]Nagisa Ishiura, Masayuki Ito, Shuzo Yajima:
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 868-875 (1990) - [c6]Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima:
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. DAC 1990: 8-13 - [c5]Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima:
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. DAC 1990: 52-57 - [c4]Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima:
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. DAC 1990: 130-135 - [c3]Hiroto Yasuura, Nagisa Ishiura:
Formal semantics of UDL/I and its applications to CAD/DA tools. ICCD 1990: 90-94
1980 – 1989
- 1989
- [c2]Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima:
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. DAC 1989: 497-502 - [c1]Hiroto Yasuura, Nagisa Ishiura:
Semantics of a Hardware Design Language for Japanese Standardization. DAC 1989: 836-839 - 1987
- [j1]Nagisa Ishiura, Hiroto Yasuura
, Shuzo Yajima:
High-Speed Logic Simulation on Vector Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(3): 305-321 (1987)
Coauthor Index
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