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ORCIDRan Zhang 0005
Person information
- affiliation: Waseda University, Graduate School of Information, Production and Systems, Kitakyushu, Japan
Other persons with the same name
- Ran Zhang — disambiguation page
- Ran Zhang 0001
![[0000-0002-6196-2890]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-6196-2890")
— Miami University, Department of Electrical and Computer Engineering, Oxford, OH, USA (and 2 more) - Ran Zhang 0002 — Jilin University, Changchun, School of Mathematics, China
- Ran Zhang 0003 — Nanyang Technological University, Interdisciplinary Graduate School, Singapore
- Ran Zhang 0004 — Beijing University of Posts and Telecommunications, State Key Laboratory of Networking and Switching Technology, China
- Ran Zhang 0006 — China University of Mining and Technology, School of Information and Control Engineering, Xuzhou, China
- Ran Zhang 0007 — Hasso Plattner Institute, Potsdam, Germany (and 1 more)
- Ran Zhang 0008 — Chinese Academy of Sciences, Computer Network Information Center, Beijing, China (and 1 more)
- Ran Zhang 0009 — University of Wisconsin-Madison, Department of Medical Physics, WI, USA
- Ran Zhang 0010 — Heilongjiang University, School of Mathematical Science, Harbin, China (and 2 more)
- Ran Zhang 0011 — University of British, Columbia School of Engineering, Faculty of Applied Science, BC, Canada (and 1 more)
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2010 – 2019
- 2015
[j4]Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. Inf. Media Technol. 10(3): 395-404 (2015)- [j3]Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. IPSJ Trans. Syst. LSI Des. Methodol. 8: 75-84 (2015) - [c4]Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe:
A length matching routing method for disordered pins in PCB design. ASP-DAC 2015: 402-407 - 2014
- [c3]Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe:
A randomized algorithm for the fixed-length routing problem. APCCAS 2014: 711-714 - 2013
- [j2]Xin Jiang, Ran Zhang, Takahiro Watanabe:
An Efficient Algorithm for 3D NoC Architecture Optimization. Inf. Media Technol. 8(2): 254-261 (2013) - [j1]Xin Jiang, Ran Zhang, Takahiro Watanabe:
An Efficient Algorithm for 3D NoC Architecture Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 6: 34-41 (2013) - [c2]Ran Zhang, Xue Wei, Takahiro Watanabe:
A sorting-based IO connection assignment for flip-chip designs. ASICON 2013: 1-4 - 2011
- [c1]Xin Jiang, Ran Zhang, Takahiro Watanabe:
An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. ASICON 2011: 535-538
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