- Wei-Chung Chen, Yi-Ping Su, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen
, Ying-Hsi Lin, Chao-Cheng Lee, Shian-Ru Lin, Tsung-Yen Tsai:
Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology. IEEE J. Solid State Circuits 50(7): 1525-1539 (2015) - Ming-Shuan Chen, Chih-Kong Ken Yang:
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50(8): 1903-1916 (2015) - Chia-Hung Chen, Yi Zhang, Tao He, Patrick Yin Chiang, Gabor C. Temes:
A Micro-Power Two-Step Incremental Analog-to-Digital Converter. IEEE J. Solid State Circuits 50(8): 1796-1808 (2015) - Taiyun Chi, Jun Luo, Song Hu, Hua Wang:
A Multi-Phase Sub-Harmonic Injection Locking Technique for Bandwidth Extension in Silicon-Based THz Signal Generation. IEEE J. Solid State Circuits 50(8): 1861-1873 (2015) - Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee:
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50(2): 573-585 (2015) - Shih-Hsiung Chien, Ting-Hsuan Hung, Szu-Yu Huang, Tai-Haur Kuo:
A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit. IEEE J. Solid State Circuits 50(11): 2524-2532 (2015) - Hyunwoo Cho, Hyungwoo Lee, Joonsung Bae, Hoi-Jun Yoo:
A 5.2 mW IEEE 802.15.6 HBC Standard Compatible Transceiver With Power Efficient Delay-Locked-Loop Based BPSK Demodulator. IEEE J. Solid State Circuits 50(11): 2549-2559 (2015) - Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits 50(3): 737-748 (2015) - Woong Choi, Gyuseong Kang, Jongsun Park:
A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder. IEEE J. Solid State Circuits 50(10): 2451-2462 (2015) - Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon:
An Energy/Illumination-Adaptive CMOS Image Sensor With Reconfigurable Modes of Operations. IEEE J. Solid State Circuits 50(6): 1438-1450 (2015) - Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015) - Ryan Clarke, Mitchell R. LeRoy, Srikumar Raman, Tuhin Guha Neogi, Russell P. Kraft, John F. McDonald:
140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology. IEEE J. Solid State Circuits 50(11): 2703-2713 (2015) - Numa Couniot, Guerric de Streel, François Botman, Angelo Kuti Lusala, Denis Flandre, David Bol:
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs. IEEE J. Solid State Circuits 50(10): 2419-2430 (2015) - Vivek De, Stephen Kosonocky, Jonathan Chang, Yogesh K. Ramadass, David Stoppa:
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions. IEEE J. Solid State Circuits 50(1): 4-9 (2015) - Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa:
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50(8): 1917-1931 (2015) - Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun:
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners. IEEE J. Solid State Circuits 50(5): 1107-1116 (2015) - Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits 50(4): 867-881 (2015) - Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu:
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. IEEE J. Solid State Circuits 50(12): 3160-3174 (2015) - Mikko Englund, Kim B. Ostman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen:
A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS. IEEE J. Solid State Circuits 50(3): 644-655 (2015) - Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden:
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters. IEEE J. Solid State Circuits 50(1): 258-269 (2015) - Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits 50(12): 3065-3076 (2015) - Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - Michael P. Flynn:
New Associate Editors. IEEE J. Solid State Circuits 50(1): 3 (2015) - Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(4): 811 (2015) - Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(6): 1335 (2015) - Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(7): 1511 (2015) - Michael P. Flynn:
New Associate Editor. IEEE J. Solid State Circuits 50(11): 2471 (2015) - Brecht François, Patrick Reynaert:
A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS. IEEE J. Solid State Circuits 50(5): 1237-1250 (2015) - Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang:
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. IEEE J. Solid State Circuits 50(8): 1932-1944 (2015)
