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ORCIDHao Cai 0001
Person information
- affiliation: Nanjing University of Aeronautics and Astronautics, College of Electronic and Information Engineering, China
- affiliation: Southeast University, National ASIC System Engineering Center, Nanjing, China
- affiliation (2013-2017): Université Paris-Saclay, European EUREKA Program CATRENERELY, Paris, France
- affiliation (PhD 2013): Télécom ParisTech, Paris, France
Other persons with the same name
- Hao Cai — disambiguation page
- Hao Cai 0002
![[0000-0002-9879-2960]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-9879-2960")
— Shantou University, College of Mathematics and Computer Science, Guangdong, China (and 1 more) - Hao Cai 0003 — Wuhan University of Technology, School of Computing, Intelligent Transportation Systems Research Center, China (and 1 more)
- Hao Cai 0004 — Memorial University of Newfoundland, Department of Computer Science, St.John's, NL, Canada
- Hao Cai 0005 — Nanjing Tech University, College of Urban Construction, China (and 1 more)
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Journal Articles
- 2024
[j51]Bo Liu, Na Xie, Qingwen Wei, Guang Yang, Chonghang Xie, Weiqiang Liu, Hao Cai:
Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4412-4425 (2024)- [j50]Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu:
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 187-200 (2024) - [j49]Xin Chen, Yuxin Bai, Hao Cai, Congyi Zhu, Xinjie Zhou, Ying Zhang, Weiqiang Liu:
Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2632-2645 (2024) - [j48]Bo Liu, Xinxiang Huang, Yang Zhang, Guang Yang, Han Yan, Chen Zhang, Zejv Li, Yuanhao Wang, Hao Cai:
Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4652-4664 (2024) - [j47]Yu Gong, Bo Liu, Hao Cai, Longxing Shi, Weiqiang Liu:
VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 837-841 (2024) - [j46]Haoran Du, You Wang, Jun Yang, Hao Cai:
Intrinsic MRAM Properties Enable Security Circuits. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1695-1700 (2024) - [j45]Bo Liu, Xuanhao Zhang, Hui Kou, Chenjie Xia, Zhen Wang, Hao Cai:
On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2819-2823 (2024) - [j44]Jia-Le Cui, Yanan Guo, Juntong Chen, Bo Liu, Hao Cai:
Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference. IEEE Trans. Emerg. Top. Comput. 12(1): 97-108 (2024) - [j43]Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu:
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 797-809 (2024) - 2023
- [j42]Zhong-Jian Bian, Bo Liu, Hao Cai:
Computing in-memory with cascaded spintronic devices for AI edge. Comput. Electr. Eng. 109(Part B): 108767 (2023) - [j41]Bo Liu, Renyuan Zhang, Qiao Shen, Zeju Li, Na Xie, Yuanhao Wang, Chonghang Xie, Hao Cai:
W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing. Comput. Electr. Eng. 111(Part A): 108921 (2023) - [j40]Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner:
Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms. IEEE Des. Test 40(3): 17-25 (2023) - [j39]Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang:
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition. IEEE Des. Test 40(3): 26-35 (2023) - [j38]Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai:
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. IEEE J. Solid State Circuits 58(3): 867-876 (2023) - [j37]Bo Liu, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang, Hao Cai:
A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 291-295 (2023) - [j36]Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao:
A Survey of MRAM-Centric Computing: From Near Memory to In Memory. IEEE Trans. Emerg. Top. Comput. 11(2): 318-330 (2023) - 2022
- [j35]Bo Liu, Zilong Zhang, Hao Cai, Reyuan Zhang, Zhen Wang, Jun Yang:
Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing. Sci. China Inf. Sci. 65(4) (2022) - [j34]Hao Cai, Xinfang Tong, Pengcheng Wu, Xinning Liu, Bo Liu:
Bit-error-rate aware sensing-error correction interaction in spintronic MRAM. J. Syst. Archit. 128: 102557 (2022) - [j33]Bo Liu, Mingyue Liu, Yongliang Zhou, Xiaofeng Hong, Hao Cai, Lirida Alves de Barros Naviner:
Writing-only in-MRAM computing paradigm for ultra-low power applications. Microprocess. Microsystems 90: 104449 (2022) - [j32]Bo Liu, Ziyu Wang, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Qiao Shen, Na Xie, Yu Gong, Zhen Wang, Jun Yang, Hao Cai:
An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4217-4228 (2022) - [j31]Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang:
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1519-1531 (2022) - [j30]Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Ziyu Wang, Yu Gong, Weiqiang Liu, Jinjiang Yang, Zhen Wang, Jun Yang:
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1571-1582 (2022) - [j29]Yu Gong, Hao Cai, Haige Wu, Wei Ge, Hao Yan, Zhen Wang, Longxing Shi, Bo Liu:
Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2928-2940 (2022) - [j28]Rashid Ali, Deming Zhang, Hao Cai, Weisheng Zhao, You Wang:
A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2712-2716 (2022) - 2021
- [j27]Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang:
A survey of in-spin transfer torque MRAM computing. Sci. China Inf. Sci. 64(6) (2021) - [j26]Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang:
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. IEEE J. Solid State Circuits 56(1): 151-164 (2021) - [j25]Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao:
Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2633-2639 (2021) - 2020
- [j24]Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu:
Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. CCF Trans. High Perform. Comput. 2(3): 282-296 (2020) - [j23]Lei Xie, Hao Cai, Chao Wang, Jun Yang:
Towards an automated design flow for memristor based VLSI circuits. Integr. 70: 21-31 (2020) - [j22]Weiwei Shan, Wentao Dai, Chuan Zhang, Hao Cai, Peiye Liu, Jun Yang, Longxing Shi:
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS. IEEE J. Solid State Circuits 55(5): 1422-1436 (2020) - [j21]Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Yongliang Zhou, Hao Cai:
Magnetic Tunnel Junction Applications. Sensors 20(1): 121 (2020) - [j20]Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang:
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1602-1614 (2020) - [j19]Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang:
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. IEEE Trans. Circuits Syst. 67-II(12): 3352-3356 (2020) - [j18]Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi:
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor. IEEE Trans. Circuits Syst. 67-I(12): 4733-4746 (2020) - 2019
- [j17]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang:
A Review of Sparse Recovery Algorithms. IEEE Access 7: 1300-1322 (2019) - [j16]Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao:
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 239-250 (2019) - [j15]Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang:
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2288-2297 (2019) - 2018
- [j14]Liuyang Zhang, Erya Deng, Hao Cai, You Wang, Lionel Torres, Aida Todri-Sanial, Youguang Zhang:
A high-reliability and low-power computing-in-memory implementation within STT-MRAM. Microelectron. J. 81: 69-75 (2018) - [j13]Nilson Maciel, Elaine Crespo Marques, Lirida A. B. Naviner, Hao Cai:
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology. Microelectron. Reliab. 88-90: 965-968 (2018) - [j12]Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang:
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3907-3917 (2018) - 2017
- [j11]Hao Cai, You Wang, Lirida Alves de Barros Naviner, Weisheng Zhao:
Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 847-857 (2017) - 2016
- [j10]Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner, You Wang, Mariem Slimani, Jean-François Naviner:
Efficient reliability evaluation methodologies for combinational circuits. Microelectron. Reliab. 64: 19-25 (2016) - [j9]You Wang, Hao Cai, Lirida A. B. Naviner, Xiaoxuan Zhao, Yue Zhang, Mariem Slimani, Jacques-Olivier Klein, Weisheng Zhao:
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. Microelectron. Reliab. 64: 26-30 (2016) - [j8]Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, You Wang, Hao Cai:
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. Microelectron. Reliab. 64: 48-53 (2016) - 2015
- [j7]Hao Cai, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit, Jean-François Naviner:
Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. Microelectron. Reliab. 55(3-4): 645-653 (2015) - [j6]Arwa Ben Dhia, Mariem Slimani, Hao Cai, Lirida A. B. Naviner:
A dual-rail compact defect-tolerant multiplexer. Microelectron. Reliab. 55(3-4): 662-670 (2015) - [j5]Ting An, Kaikai Liu, Hao Cai, Lirida A. B. Naviner:
Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method. Microelectron. Reliab. 55(3-4): 696-703 (2015) - [j4]Hao Cai, You Wang, Lirida A. B. Naviner, W. S. Zhao:
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology. Microelectron. Reliab. 55(9-10): 1323-1327 (2015) - [j3]You Wang, Hao Cai, Lirida A. B. Naviner, Yue Zhang, Jacques-Olivier Klein, Weisheng Zhao:
Compact thermal modeling of spin transfer torque magnetic tunnel junction. Microelectron. Reliab. 55(9-10): 1649-1653 (2015) - 2012
- [j2]Hao Cai, Hervé Petit, Jean-François Naviner:
A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. J. Low Power Electron. 8(5): 697-705 (2012) - 2011
- [j1]Hao Cai, Hervé Petit, Jean-François Naviner:
Reliability aware design of low power continuous-time sigma-delta modulator. Microelectron. Reliab. 51(9-11): 1449-1453 (2011)
Conference and Workshop Papers
- 2024
- [c53]Bo Liu, Qingwen Wei, Yang Zhang, Xingyu Xu, Zihan Zou, Xinxiang Huang, Xin Si, Hao Cai:
FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. DAC 2024: 144:1-144:6 - [c52]Xuanhao Zhang, Hui Kou, Chenjie Xia, Hao Cai, Bo Liu:
Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network. ICASSP 2024: 1-5 - [c51]Chenjie Xia, Xuanhao Zhang, Zihan Zou, Hao Cai, Bo Liu:
Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. ISCAS 2024: 1 - [c50]Rong Zhou, Bo Liu, Xin Si, Hao Cai:
Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory. ISCAS 2024: 1-5 - [c49]An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si:
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC 2024: 570-572 - [c48]Zhenghan Fang, Lirida Naviner, Wen Wang, Wei Le, Hao Cai:
Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching. SBCCI 2024: 1-5 - 2023
- [c47]Xingyu Xu, Qingwen Wei, Yang Zhang, Hao Cai, Bo Liu:
Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs. CASES 2023: 3-4 - [c46]You Wang, Yefan Xu, Chaoyue Zhang, Yu Gong, Hao Cai, Weiqiang Liu:
Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits. ICTA 2023: 65-66 - [c45]Qingwen Wei, Yang Zhang, Xingyu Xu, Hao Cai, Bo Liu:
An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis. ICTA 2023: 150-151 - [c44]An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC 2023: 128-129 - [c43]Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan:
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. ISSCC 2023: 500-501 - 2022
- [c42]Bo Liu, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang:
A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. DATE 2022: 196-201 - [c41]Juntong Chen, Hao Cai, Bo Liu, Jun Yang:
Triple-Skipping Near-MRAM Computing Framework for AIoT Era. DATE 2022: 1401-1406 - [c40]Qiao Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao:
A CGP-based Efficient Approximate Multiplier with Error Compensation. ICTA 2022: 48-49 - [c39]Xuanhao Zhang, Haige Wu, Renyuan Zhang, Zihang Xu, Hao Zhang, Bo Liu, Hao Cai:
A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization. ICTA 2022: 160-161 - [c38]Bo Liu, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Ziyu Wang, Haige Wu, Hao Cai:
A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing. ISCAS 2022: 2102-2106 - [c37]You Wang, Bi Wu, Hao Cai, Weiqiang Liu:
Low-cost stochastic number generator based on MRAM for stochastic computing. NANOARCH 2022: 20:1-20:5 - 2021
- [c36]You-You Zhang, Lirida A. B. Naviner, Hao Cai:
Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM. ASICON 2021: 1-4 - [c35]Bo Liu, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai:
A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition. DATE 2021: 495-500 - [c34]Zhong-Jian Bian, Yanan Guo, Bo Liu, Hao Cai:
In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN. ICTA 2021: 141-142 - [c33]Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai:
Cryogenic In-MRAM Computing. NANOARCH 2021: 1-6 - [c32]Yu-ang Wu, Lirida A. B. Naviner, Hao Cai:
Hybrid MTJ-CMOS Integration for Sigma-Delta ADC. NANOARCH 2021: 1-5 - 2020
- [c31]Zhengyi Hou, You Wang, Deming Zhang, Chengzhi Wang, Hao Cai:
A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM. ACM Great Lakes Symposium on VLSI 2020: 65-70 - [c30]Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang, Zhen Wang:
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN. ACM Great Lakes Symposium on VLSI 2020: 193-198 - [c29]Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong, Zhen Wang:
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing. ACM Great Lakes Symposium on VLSI 2020: 271-275 - [c28]Nilson Maciel, Elaine Crespo Marques, Lírida A. B. Naviner, Hao Cai:
Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism. ICECS 2020: 1-4 - [c27]Bo Liu, Hao Cai, Yu Gong, Wentao Zhu, Yan Li, Wei Ge, Zhen Wang:
Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing. ISCAS 2020: 1-5 - 2019
- [c26]Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao:
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. ACM Great Lakes Symposium on VLSI 2019: 135-140 - [c25]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang:
Deep Learning Approaches for Sparse Recovery in Compressive Sensing. ISPA 2019: 129-134 - [c24]Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao:
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. ISVLSI 2019: 111-115 - [c23]Mingyue Liu, Hao Cai, Menglin Han, Lei Xie, Jun Yang, Lirida A. B. Naviner:
Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. NANOARCH 2019: 1-6 - [c22]Lei Xie, Hao Cai, Jun Yang:
REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing. NANOARCH 2019: 1-4 - [c21]Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang:
A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. NANOARCH 2019: 1-6 - [c20]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang:
Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery. SiPS 2019: 324-329 - 2018
- [c19]Menglin Han, Hao Cai, Jun Yang, Lirida A. B. Naviner, You Wang, Weisheng Zhao:
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. APCCAS 2018: 386-389 - [c18]Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao:
Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. DCIS 2018: 1-5 - [c17]You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner:
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. ACM Great Lakes Symposium on VLSI 2018: 403-408 - [c16]Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang:
Compressed Sensing for Wideband HF Channel Estimation. ICFSP 2018: 1-5 - [c15]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao:
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. ISCAS 2018: 1-5 - [c14]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao:
MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ISVLSI 2018: 263-268 - [c13]Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao:
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. ISVLSI 2018: 275-280 - 2017
- [c12]Hao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao:
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. ACM Great Lakes Symposium on VLSI 2017: 23-28 - [c11]Hao Cai, You Wang, Lirida A. B. Naviner, Weisheng Zhao:
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. ISVLSI 2017: 57-61 - 2016
- [c10]You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao:
A novel circuit design of true random number generator using magnetic tunnel junction. NANOARCH 2016: 123-128 - [c9]Hao Cai, You Wang, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao:
Approximate computing in MOS/spintronic non-volatile full-adder. NANOARCH 2016: 203-208 - 2015
- [c8]Lirida Alves de Barros Naviner, Hao Cai, You Wang, Weisheng Zhao, Arwa Ben Dhia:
Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction. NEWCAS 2015: 1-4 - 2014
- [c7]Lirida A. B. Naviner, Kaikai Liu, Hao Cai, Jean-François Naviner:
Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. ICICDT 2014: 1-4 - [c6]Ting An, Hao Cai, Lirida Alves de Barros Naviner:
Simulation study of aging in CMOS binary adders. MIPRO 2014: 51-55 - [c5]Hao Cai, Kaikai Liu, Lirida Alves de Barros Naviner:
Reliability-aware delay faults evaluation of CMOS flip-flops. MIXDES 2014: 385-389 - [c4]Ting An, Kaikai Liu, Hao Cai, Lirida Alves de Barros Naviner:
Efficient implementation for accurate analysis of CED circuits against multiple faults. MIXDES 2014: 436-440 - 2013
- [c3]Kaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit:
Reliability analysis of combinational circuits with the influences of noise and single-event transients. DFTS 2013: 218-223 - [c2]Kaikai Liu, Ting An, Hao Cai, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit:
A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. EUROCON 2013: 1829-1836 - [c1]Hao Cai, Hervé Petit, Jean-François Naviner:
A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts. NEWCAS 2013: 1-4
Parts in Books or Collections
- 2022
- [p2]You Wang, Hao Cai, Kaili Zhang, Bo Wu, Bo Liu, Deming Zhang, Weisheng Zhao:
Spintronic Solutions for Approximate Computing. Approximate Computing 2022: 99-117 - [p1]Bo Liu, Hao Cai, Zhen Wang, Jun Yang:
Approximate Computing for Energy-Constrained DNN-Based Speech Recognition. Approximate Computing 2022: 451-480
Informal and Other Publications
- 2021
- [i1]Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang:
Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. CoRR abs/2110.03937 (2021)
Coauthor Index
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