• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 5,485 matches

• 2024
• 
  Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
  Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 592-596 (2024)
• 
  Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
  Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2154-2158 (2024)
• 
  Meysam Akbari, Kea-Tiong Tang:
  The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1801-1811 (2024)
• 
  Vassilis Alimisis, Emmanouil Anastasios Serlis, Andreas Papathanasiou, Nikolaos P. Eleftheriou, Paul P. Sotiriadis:
  Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 1969-1982 (2024)
• 
  Abdulaziz Alshaya, Sudhakar Pamarti, Christos Papavassiliou:
  FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 103-115 (2024)
• 
  Isa H. Altoobaji, Ahmad Hassan, Mohamed Ali, Yves Audet, Ahmed Lakhssassi:
  A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital Isolator With 1.9-ns Propagation Delay. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 952-956 (2024)
• 
  Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song:
  A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1169-1172 (2024)
• 
  Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou:
  Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 283-290 (2024)
• 
  Md Toufiq Hasan Anik, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi:
  On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 911-924 (2024)
• 
  Seyedarmin Azizi, Mahdi Nazemi, Mehdi Kamal, Massoud Pedram:
  Low-Precision Mixed-Computation Models for Inference on Edge. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1414-1422 (2024)
• 
  Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou:
  Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 128-136 (2024)
• 
  Robert Balas, Alessandro Ottaviano, Luca Benini:
  CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1032-1044 (2024)
• 
  Tianyou Bao, Pengzhou He, Shi Bai, Jiafeng Xie:
  TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 870-882 (2024)
• 
  Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl:
  A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 231-244 (2024)
• 
  Yasong Cao, Mei Wen, Zhongdi Luo, Xin Ju, Haolan Huang, Junzhong Shen, Haiyan Chen:
  ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1590-1601 (2024)
• 
  Shu-Yu Chang, Shi-Yu Huang:
  A Check-and-Balance Scheme in Multiphase Delay-Locked Loop. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1253-1262 (2024)
• 
  Ke Chang, Qian Xing, Guoliang Jia, Yang Pu, Yan Wang, Yuxin Wang, Yanlong Zhang, Guohe Zhang:
  An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 200-204 (2024)
• 
  Liang Chang, Xin Zhao, Ting Yue, Xi Yang, Chenglong Li, Shuisheng Lin, Jun Zhou:
  IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 256-268 (2024)
• 
  Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis:
  A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1616-1629 (2024)
• 
  Arunkumar P. Chavan, Shrish Shrinath Vaidya, Sanket M. Mantrashetti, Abhishek Gurunath Dastikopp, Kishan S. Murthy, H. V. Ravish Aradhya, Prakash Pawar:
  A Novel TriNet Architecture for Enhanced Analog IC Design Automation. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2046-2059 (2024)
• 
  Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong:
  A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 848-859 (2024)
• 
  Yanhang Chen, Siji Huang, Qifeng Huang, Yifei Fan, Jie Yuan:
  The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 1983-1992 (2024)
• 
  Bofan Chen, Zhiqun Li, Wei Shi, Yan Yao, Zhi-Ying Xia, Bing-Yan Qiu, Hao Ji:
  A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 530-541 (2024)
• 
  Fan Chen, Wei Li, Chuangguo Wang, Yunyou Pu, Xingyu Ma, Shijiao Dong, Yun Wang, Hongtao Xu:
  Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1578-1589 (2024)
• 
  Li-De Chen, Li-Qun Weng, Hao-Chien Cheng, An-Yu Cheng, Kai-Ping Lin, Chao-Tsung Huang:
  VLSI Design of Light-Field Factorization for Dual-Layer Factored Display. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2093-2106 (2024)
• 
  Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding:
  Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 372-381 (2024)
• 
  Young-Kyun Cho:
  A Dual-Mode Continuous-Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1754-1758 (2024)
• 
  Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo:
  Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 245-255 (2024)
• 
  Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu:
  A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 480-484 (2024)
• 
  Joseph Franklin Clements, Yingjie Lao:
  Reliable Hardware Watermarks for Deep Learning Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 752-762 (2024)

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