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@article{DBLP:journals/tvlsi/AhmadiAKA24,
author = {Kasra Ahmadi and
Saeed Aghapour and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Efficient Error Detection Schemes for {ECSM} Window Method Benchmarked
on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {592--596},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3341147},
doi = {10.1109/TVLSI.2023.3341147},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmadiAKA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmadiAKA24a,
author = {Kasra Ahmadi and
Saeed Aghapour and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Efficient Error Detection Cryptographic Architectures Benchmarked
on FPGAs for Montgomery Ladder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2154--2158},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3419700},
doi = {10.1109/TVLSI.2024.3419700},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmadiAKA24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AkbariT24,
author = {Meysam Akbari and
Kea{-}Tiong Tang},
title = {The Conjugated Current Mirrors: {A} General Enhancement in Transconductance
Amplifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1801--1811},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3439525},
doi = {10.1109/TVLSI.2024.3439525},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AkbariT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlimisisSPES24,
author = {Vassilis Alimisis and
Emmanouil Anastasios Serlis and
Andreas Papathanasiou and
Nikolaos P. Eleftheriou and
Paul P. Sotiriadis},
title = {Power-Efficient Analog Hardware Architecture of the Learning Vector
Quantization Algorithm for Brain Tumor Classification},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {1969--1982},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3447903},
doi = {10.1109/TVLSI.2024.3447903},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlimisisSPES24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlshayaPP24,
author = {Abdulaziz Alshaya and
Sudhakar Pamarti and
Christos Papavassiliou},
title = {{FPGA} Crystal Oscillator Circuit Emulation Based on Wave Digital
Filter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {103--115},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3305597},
doi = {10.1109/TVLSI.2023.3305597},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlshayaPP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AltoobajiHAAL24,
author = {Isa H. Altoobaji and
Ahmad Hassan and
Mohamed Ali and
Yves Audet and
Ahmed Lakhssassi},
title = {A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital
Isolator With 1.9-ns Propagation Delay},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {952--956},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3344413},
doi = {10.1109/TVLSI.2023.3344413},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AltoobajiHAAL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AnYAKJHS24,
author = {Jongchan An and
Seung{-}Myeong Yu and
Gwangmyeong An and
Bongsu Kim and
Hyunsu Jang and
Sewook Hwang and
Junyoung Song},
title = {A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery
Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1169--1172},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3377723},
doi = {10.1109/TVLSI.2024.3377723},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AnYAKJHS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AnZWYLGLTWHYFLLD24,
author = {Junjie An and
Zhidao Zhou and
Linfang Wang and
Wang Ye and
Weizeng Li and
Hanghang Gao and
Zhi Li and
Jinghui Tian and
Yan Wang and
Hongyang Hu and
Jinshan Yue and
Lingyan Fan and
Shibing Long and
Qi Liu and
Chunmeng Dou},
title = {Write-Verify-Free {MLC} {RRAM} Using Nonbinary Encoding for {AI} Weight
Storage at the Edge},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {283--290},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3318744},
doi = {10.1109/TVLSI.2023.3318744},
timestamp = {Tue, 13 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AnZWYLGLTWHYFLLD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AnikDGK24,
author = {Md Toufiq Hasan Anik and
Jean{-}Luc Danger and
Sylvain Guilley and
Naghmeh Karimi},
title = {On the Resiliency of Protected Masked S-Boxes Against Template Attack
in the Presence of Temperature and Aging Misalignments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {911--924},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3374257},
doi = {10.1109/TVLSI.2024.3374257},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AnikDGK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AyesF24,
author = {Andres Ayes and
Eby G. Friedman},
title = {Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2394--2397},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3448374},
doi = {10.1109/TVLSI.2024.3448374},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AyesF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AziziNKP24,
author = {Seyedarmin Azizi and
Mahdi Nazemi and
Mehdi Kamal and
Massoud Pedram},
title = {Low-Precision Mixed-Computation Models for Inference on Edge},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1414--1422},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409640},
doi = {10.1109/TVLSI.2024.3409640},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AziziNKP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaiXXWWZ24,
author = {Na Bai and
Xin Xiao and
Yaohua Xu and
Yi Wang and
Liang Wang and
Xinjie Zhou},
title = {Soft-Error-Aware {SRAM} With Multinode Upset Tolerance for Aerospace
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {128--136},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3328717},
doi = {10.1109/TVLSI.2023.3328717},
timestamp = {Fri, 04 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaiXXWWZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalasOB24,
author = {Robert Balas and
Alessandro Ottaviano and
Luca Benini},
title = {{CV32RT:} Enabling Fast Interrupt and Context Switching for {RISC-V}
Microcontrollers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1032--1044},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3377130},
doi = {10.1109/TVLSI.2024.3377130},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BalasOB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaoHBX24,
author = {Tianyou Bao and
Pengzhou He and
Shi Bai and
Jiafeng Xie},
title = {{TINA:} TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based
{PQC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {870--882},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3341037},
doi = {10.1109/TVLSI.2023.3341037},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaoHBX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BroschPGS24,
author = {Manuel Brosch and
Matthias Probst and
Matthias Glaser and
Georg Sigl},
title = {A Masked Hardware Accelerator for Feed-Forward Neural Networks With
Fixed-Point Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {231--244},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3340553},
doi = {10.1109/TVLSI.2023.3340553},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BroschPGS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoWLJHSC24,
author = {Yasong Cao and
Mei Wen and
Zhongdi Luo and
Xin Ju and
Haolan Huang and
Junzhong Shen and
Haiyan Chen},
title = {{ABS:} Accumulation Bit-Width Scaling Method for Designing Low-Precision
Tensor Core},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1590--1601},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3414260},
doi = {10.1109/TVLSI.2024.3414260},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoWLJHSC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangH24,
author = {Shu{-}Yu Chang and
Shi{-}Yu Huang},
title = {A Check-and-Balance Scheme in Multiphase Delay-Locked Loop},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1253--1262},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3393615},
doi = {10.1109/TVLSI.2024.3393615},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangXJPWWZZ24,
author = {Ke Chang and
Qian Xing and
Guoliang Jia and
Yang Pu and
Yan Wang and
Yuxin Wang and
Yanlong Zhang and
Guohe Zhang},
title = {An Improved {DEM} for Multibit {DT} {\(\Sigma\)}{\(\Delta\)}Ms Based
on Poles Splitting Technique and Segmented {VQ}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {200--204},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3318230},
doi = {10.1109/TVLSI.2023.3318230},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangXJPWWZZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangZYYLLZ24,
author = {Liang Chang and
Xin Zhao and
Ting Yue and
Xi Yang and
Chenglong Li and
Shuisheng Lin and
Jun Zhou},
title = {{IPOCIM:} Artificial Intelligent Architecture Design Space Exploration
With Scalable Ping-Pong Computing-in-Memory Macro},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {256--268},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3330648},
doi = {10.1109/TVLSI.2023.3330648},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangZYYLLZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChatziantoniouTTKP24,
author = {Panagiotis Chatziantoniou and
Antonis Tsigkanos and
Dimitris Theodoropoulos and
Nektarios Kranitis and
Antonis M. Paschalis},
title = {A Parallel Architecture and Implementation for Near-Lossless Hyperspectral
Image Compression Based on {CCSDS} 123.0-B-2 With Scalable Data-Rate
Performance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1616--1629},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3415505},
doi = {10.1109/TVLSI.2024.3415505},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChatziantoniouTTKP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChavanVMDMAP24,
author = {Arunkumar P. Chavan and
Shrish Shrinath Vaidya and
Sanket M. Mantrashetti and
Abhishek Gurunath Dastikopp and
Kishan S. Murthy and
H. V. Ravish Aradhya and
Prakash Pawar},
title = {A Novel TriNet Architecture for Enhanced Analog {IC} Design Automation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2046--2059},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3452032},
doi = {10.1109/TVLSI.2024.3452032},
timestamp = {Mon, 09 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChavanVMDMAP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenDH24,
author = {Chao{-}Yu Chen and
Yan{-}Siou Dai and
Hao{-}Chiao Hong},
title = {A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding
Scheme and Analog Computing in Low-Leakage 8T {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {848--859},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3368849},
doi = {10.1109/TVLSI.2024.3368849},
timestamp = {Sat, 08 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenDH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHHFY24,
author = {Yanhang Chen and
Siji Huang and
Qifeng Huang and
Yifei Fan and
Jie Yuan},
title = {The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution
{SAR} ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {1983--1992},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3458071},
doi = {10.1109/TVLSI.2024.3458071},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHHFY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLSYXQJ24,
author = {Bofan Chen and
Zhiqun Li and
Wei Shi and
Yan Yao and
Zhi{-}Ying Xia and
Bing{-}Yan Qiu and
Hao Ji},
title = {A 6-18-GHz 6-bit Full-360{\textdegree} Vector-Sum Phase Shifter With
Low Error in 40-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {530--541},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3331508},
doi = {10.1109/TVLSI.2023.3331508},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLSYXQJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLWPMDWX24,
author = {Fan Chen and
Wei Li and
Chuangguo Wang and
Yunyou Pu and
Xingyu Ma and
Shijiao Dong and
Yun Wang and
Hongtao Xu},
title = {Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference
Canceller},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1578--1589},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3410010},
doi = {10.1109/TVLSI.2024.3410010},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLWPMDWX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWCCLH24,
author = {Li{-}De Chen and
Li{-}Qun Weng and
Hao{-}Chien Cheng and
An{-}Yu Cheng and
Kai{-}Ping Lin and
Chao{-}Tsung Huang},
title = {{VLSI} Design of Light-Field Factorization for Dual-Layer Factored
Display},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2093--2106},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3414262},
doi = {10.1109/TVLSI.2024.3414262},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWCCLH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenYCWD24,
author = {Zhuojun Chen and
Wenhao Yang and
Jinghang Chen and
Zujun Wang and
Ding Ding},
title = {Improving Radiation Reliability of SRAM-Based Physical Unclonable
Function With Self-Healing and Pre-Irradiation Masking Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {372--381},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3332010},
doi = {10.1109/TVLSI.2023.3332010},
timestamp = {Mon, 30 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenYCWD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Cho24,
author = {Young{-}Kyun Cho},
title = {A Dual-Mode Continuous-Time Sigma-Delta Modulator With a Reconfigurable
Loop Filter Based on a Single Op-Amp Resonator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1754--1758},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3414298},
doi = {10.1109/TVLSI.2024.3414298},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Cho24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiHCS24,
author = {Sureum Choi and
Daejin Han and
Chanyeong Choi and
Yeongkyo Seo},
title = {Layout-Aware Area Optimization of Transposable {STT-MRAM} for a Processing-In-Memory
System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {245--255},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3336804},
doi = {10.1109/TVLSI.2023.3336804},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiHCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChouCL24,
author = {Po{-}Yuan Chou and
Wei{-}Ming Chen and
Shen{-}Iuan Liu},
title = {A 16-Gb/s Baud-Rate {CDR} Circuit With One-Tap Speculative {DFE} and
Wide Frequency Capture Range},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {480--484},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3353197},
doi = {10.1109/TVLSI.2024.3353197},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChouCL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ClementsL24,
author = {Joseph Franklin Clements and
Yingjie Lao},
title = {Reliable Hardware Watermarks for Deep Learning Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {752--762},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3360240},
doi = {10.1109/TVLSI.2024.3360240},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ClementsL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CookeN24,
author = {Mitchell Cooke and
Nicola Nicolici},
title = {Thresholding Decision-Directed Descent {(T3D):} {A} Tuning Solution
for {DDR5} {DRAM} DFEs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2060--2073},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3435419},
doi = {10.1109/TVLSI.2024.3435419},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CookeN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CoulonBX24,
author = {Samuel Coulon and
Tianyou Bao and
Jiafeng Xie},
title = {{FELIX:} FPGA-Based Scalable and Lightweight Accelerator for Large
Integer Extended {GCD}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1684--1695},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3417016},
doi = {10.1109/TVLSI.2024.3417016},
timestamp = {Mon, 09 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CoulonBX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CromjonghTHA24,
author = {Casper Cromjongh and
Yongding Tian and
H. Peter Hofstee and
Zaid Al{-}Ars},
title = {Hardware-Accelerator Design by Composition: Dataflow Component Interfaces
With Tydi-Chisel},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2281--2292},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3461330},
doi = {10.1109/TVLSI.2024.3461330},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CromjonghTHA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaiLZQHYW24,
author = {Yuan Dai and
Jingyuan Li and
Qilong Zhu and
Yunhui Qiu and
Yihan Hu and
Wenbo Yin and
Lingli Wang},
title = {{HETA:} {A} Heterogeneous Temporal {CGRA} Modeling and Design Space
Exploration via Bayesian Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {505--518},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3344536},
doi = {10.1109/TVLSI.2023.3344536},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaiLZQHYW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DarabiHPCGT24,
author = {Nastaran Darabi and
Maeesha Binte Hashem and
Hongyi Pan and
Ahmet Enis {\c{C}}etin and
Wilfred Gomes and
Amit Ranjan Trivedi},
title = {ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency
Transformation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {991--1003},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3375111},
doi = {10.1109/TVLSI.2024.3375111},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DarabiHPCGT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DelwarSALR24,
author = {Tahesin Samira Delwar and
Abrar Siddique and
Unal Aras and
Yang{-}Won Lee and
Jee{-}Youl Ryu},
title = {A {\(\mu\)}-GA Oriented ANN-Driven: Parameter Extraction of 5G {CMOS}
Power Amplifier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1569--1577},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3414584},
doi = {10.1109/TVLSI.2024.3414584},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DelwarSALR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EleftheriadisCK24,
author = {Charalampos Eleftheriadis and
Georgios Chatzitsompanis and
Georgios Karakonstantis},
title = {Enabling Voltage Over-Scaling in Multiplierless {DSP} Architectures
via Algorithm-Hardware Co-Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {219--230},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3308607},
doi = {10.1109/TVLSI.2023.3308607},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EleftheriadisCK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErcanXZLYZ24,
author = {Renas Ercan and
Yunjia Xia and
Yunyi Zhao and
Rui C. V. Loureiro and
Shufan Yang and
Hubin Zhao},
title = {An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts
Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {763--773},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3356161},
doi = {10.1109/TVLSI.2024.3356161},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ErcanXZLYZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FanWPCLSC24,
author = {Zipeng Fan and
Sanqian Wang and
Xueting Pu and
Yuting Cong and
Yuan Liu and
Xiubao Sui and
Qian Chen},
title = {DLB-CNet: Difference Learning-Based Convolution Network for Building
Change Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2037--2045},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3438728},
doi = {10.1109/TVLSI.2024.3438728},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FanWPCLSC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangZ24,
author = {Xu Fang and
Xiaofeng Zhao},
title = {A Post-Bond {ILV} Test Method in Monolithic 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2377--2388},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3450452},
doi = {10.1109/TVLSI.2024.3450452},
timestamp = {Sat, 11 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FathP24,
author = {Patrick Fath and
Harald Pretl},
title = {A 370-nW Bio-AFE With 2.9-{\(\mu\)} Vrms Input Noise in an Octa-Channel
System-in-Package for Multimode Bio-Signal Acquisition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2173--2185},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3430059},
doi = {10.1109/TVLSI.2024.3430059},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FathP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FeylingMWLY24,
author = {Fredrik Feyling and
Hampus Malmberg and
Carsten Wulff and
Hans{-}Andrea Loeliger and
Trond Ytterdal},
title = {Design and Analysis of the Leapfrog Control-Bounded {A/D} Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {79--88},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3320279},
doi = {10.1109/TVLSI.2023.3320279},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FeylingMWLY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GagliardiSPBD24,
author = {Francesco Gagliardi and
Danilo Scintu and
Massimo Piotto and
Paolo Bruschi and
Michele Dei},
title = {Static-Linearity Enhancement Techniques for Digital-to-Analog Converters
Exploiting Optimal Arrangements of Unit Elements},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2243--2256},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3495558},
doi = {10.1109/TVLSI.2024.3495558},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GagliardiSPBD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaurT24,
author = {Bhaskar Gaur and
Himanshu Thapliyal},
title = {Novel Optimized Designs of Modulo 2\({}^{\mbox{n}}\)+1 Adder for Quantum
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1759--1763},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3418930},
doi = {10.1109/TVLSI.2024.3418930},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaurT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GebremichealE24,
author = {Mizan Abraha Gebremicheal and
Ibrahim M. Elfadel},
title = {Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption
Overhead},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1661--1671},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3418713},
doi = {10.1109/TVLSI.2024.3418713},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GebremichealE24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhashghaiG24,
author = {M. Ghashghai and
M. B. Ghaznavi{-}Ghoushchi},
title = {Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing
Signal Flow Graph Domain Inspection Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1792--1800},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3426516},
doi = {10.1109/TVLSI.2024.3426516},
timestamp = {Tue, 15 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhashghaiG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhoshMRG24,
author = {Shouharda Ghosh and
Pramod Kumar Meher and
Dwaipayan Ray and
Nithin V. George},
title = {Low Complexity Design of Logistic Distance Metric Adaptive Filter
for Impulsive Noise Environments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1409--1413},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3407732},
doi = {10.1109/TVLSI.2024.3407732},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhoshMRG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhoshSCBSGVRKU24,
author = {Agnimesh Ghosh and
Andrei Spelman and
Tze Hin Cheung and
Dhanashree Boopathy and
Kari Stadius and
Manil Dev Gomony and
Mikko Valkama and
Jussi Ryyn{\"{a}}nen and
Marko Kosunen and
Vishnu Unnikrishnan},
title = {Reconfigurable Signal Processing and {DSP} Hardware Generator for
5G and Beyond Transmitters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {4--15},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3326159},
doi = {10.1109/TVLSI.2023.3326159},
timestamp = {Fri, 18 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhoshSCBSGVRKU24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuptaLC24,
author = {Shourya Gupta and
Shuo Li and
Benton H. Calhoun},
title = {Scalable All-Analog LDOs With Reduced Input Offset Variability Using
Digital Synthesis Flow in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {190--194},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3328978},
doi = {10.1109/TVLSI.2023.3328978},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuptaLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaoWLZZLLPZZDLW24,
author = {Licai Hao and
Yaling Wang and
Yunlong Liu and
Shiyu Zhao and
Xinyi Zhang and
Yang Li and
Wenjuan Lu and
Chunyu Peng and
Qiang Zhao and
Yongliang Zhou and
Chenghu Dai and
Zhiting Lin and
Xiulong Wu},
title = {Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {883--896},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3357312},
doi = {10.1109/TVLSI.2024.3357312},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HaoWLZZLLPZZDLW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaoZDZLPZLW24,
author = {Licai Hao and
Xinyi Zhang and
Chenghu Dai and
Qiang Zhao and
Wenjuan Lu and
Chunyu Peng and
Yongliang Zhou and
Zhiting Lin and
Xiulong Wu},
title = {Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity
Design and Source-Isolation Technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {597--608},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3342982},
doi = {10.1109/TVLSI.2023.3342982},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HaoZDZLPZLW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeXHWCLLS24,
author = {Luchang He and
Chenchen Xie and
Zhao Han and
Qingyu Wu and
Houpeng Chen and
Shibing Long and
Xi Li and
Zhitang Song},
title = {A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow
Typical Quiescent Current for Emerging Nonvolatile Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1400--1408},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3383044},
doi = {10.1109/TVLSI.2024.3383044},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeXHWCLLS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeXWXCDLS24,
author = {Luchang He and
Chenchen Xie and
Qingyu Wu and
Siqiu Xu and
Houpeng Chen and
Xing Ding and
Xi Li and
Zhitang Song},
title = {A Low-Cost Quadruple-Node-Upsets Resilient Latch Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1930--1939},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3430224},
doi = {10.1109/TVLSI.2024.3430224},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeXWXCDLS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HirnerMR24,
author = {Florian Hirner and
Ahmet Can Mert and
Sujoy Sinha Roy},
title = {Proteus: {A} Pipelined {NTT} Architecture Generator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1228--1238},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3377366},
doi = {10.1109/TVLSI.2024.3377366},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HirnerMR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HongSW24,
author = {Baoling Hong and
Haikuo Shao and
Zhongfeng Wang},
title = {A Low Complexity Online Learning Approximate Message Passing Detector
for Massive {MIMO}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1273--1284},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3392688},
doi = {10.1109/TVLSI.2024.3392688},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HongSW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HouBK24,
author = {Xiaolu Hou and
Jakub Breier and
Mladen Kovacevic},
title = {Another Look at Side-Channel-Resistant Encoding Schemes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1559--1563},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3390614},
doi = {10.1109/TVLSI.2024.3390614},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HouBK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuLWL24,
author = {Xiao Hu and
Zhihao Li and
Zhongfeng Wang and
Xianhui Lu},
title = {{ALT:} Area-Efficient and Low-Latency {FPGA} Design for Torus Fully
Homomorphic Encryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {645--657},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3353374},
doi = {10.1109/TVLSI.2024.3353374},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuLWL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangBCHFY24,
author = {Siji Huang and
Debajit Basak and
Yanhang Chen and
Qifeng Huang and
Yifei Fan and
Jie Yuan},
title = {An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved {SAR}
{ADC} With a Centralized Sampling Frontend},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1195--1204},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3392611},
doi = {10.1109/TVLSI.2024.3392611},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangBCHFY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangHCFY24,
author = {Qifeng Huang and
Siji Huang and
Yanhang Chen and
Yifei Fan and
Jie Yuan},
title = {An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step
{SC} {DAC} Achieving 2.67{\%} Jitter Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1841--1851},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3417015},
doi = {10.1109/TVLSI.2024.3417015},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangHCFY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangLXLLL24,
author = {Haitong Huang and
Cheng Liu and
Xinghua Xue and
Bo Liu and
Huawei Li and
Xiaowei Li},
title = {{MRFI:} An Open-Source Multiresolution Fault Injection Framework for
Neural Network Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1325--1335},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3384404},
doi = {10.1109/TVLSI.2024.3384404},
timestamp = {Tue, 23 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangLXLLL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangR24,
author = {Yu{-}Kai Huang and
Saul Rodriguez},
title = {Noise Analysis and Design Methodology of Chopper Amplifiers With Analog
DC-Servo Loop for Biopotential Acquisition Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {55--67},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3315417},
doi = {10.1109/TVLSI.2023.3315417},
timestamp = {Fri, 08 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangWZY24,
author = {Pengcheng Huang and
Yaohua Wang and
Zhenyu Zhao and
Daheng Yue},
title = {{CAUTS:} Clock Tree Optimization via Skewed Cells With Complementary
Asymmetrical Uniform Transistor Sizing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {137--149},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3328592},
doi = {10.1109/TVLSI.2023.3328592},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangWZY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuiLWLZM24,
author = {YaJuan Hui and
Qingzhen Li and
Leimin Wang and
Cheng Liu and
Deming Zhang and
Xiangshui Miao},
title = {In-Memory Wallace Tree Multipliers Based on Majority Gates Within
Voltage-Gated {SOT-MRAM} Crossbar Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {497--504},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3350151},
doi = {10.1109/TVLSI.2024.3350151},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuiLWLZM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HungCBC24,
author = {Shao{-}Chun Hung and
Arjun Chaudhuri and
Sanmitra Banerjee and
Krishnendu Chakrabarty},
title = {Fault Diagnosis for Resistive Random Access Memory and Monolithic
Inter-Tier Vias in Monolithic 3-D Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1336--1349},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3380549},
doi = {10.1109/TVLSI.2024.3380549},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HungCBC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HyunJS24,
author = {Daijoon Hyun and
Younggwang Jung and
Youngsoo Shin},
title = {Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations
and Routing DRVs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {823--834},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3364519},
doi = {10.1109/TVLSI.2024.3364519},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HyunJS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/InayatUC24,
author = {Kashif Inayat and
Inayat Ullah and
Jaeyong Chung},
title = {Factored Systolic Arrays Based on Radix-8 Multiplication for Machine
Learning Acceleration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1205--1215},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3378197},
doi = {10.1109/TVLSI.2024.3378197},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/InayatUC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JamadiCT24,
author = {Behdad Jamadi and
Shiuh{-}Hua Wood Chiang and
Armin Tajalli},
title = {Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1364--1368},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3368355},
doi = {10.1109/TVLSI.2024.3368355},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JamadiCT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JanvejaPDPT24,
author = {Meenali Janveja and
Rushik Parmar and
Srichandan Dash and
Jan Pidanic and
Gaurav Trivedi},
title = {A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable
Healthcare Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1672--1683},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3413584},
doi = {10.1109/TVLSI.2024.3413584},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JanvejaPDPT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JelcicovaKAS24,
author = {Zuzana Jelcicov{\'{a}} and
Evangelia Kasapaki and
Oskar Andersson and
Jens Spars{\o}},
title = {PeakEngine: {A} Deterministic On-the-Fly Pruning Neural Network Accelerator
for Hearing Instruments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {150--163},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3300910},
doi = {10.1109/TVLSI.2023.3300910},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JelcicovaKAS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiePDWZY24,
author = {Musha Ji'e and
Hongxin Peng and
Shukai Duan and
Lidan Wang and
Fengqing Zhang and
Dengwei Yan},
title = {Design and {FPGA} Implementation of Grid-Scroll Hamiltonian Conservative
Chaotic Flows With a Line Equilibrium},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {658--668},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3361889},
doi = {10.1109/TVLSI.2024.3361889},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JiePDWZY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JokiniemiRVKSR24,
author = {Kimi Jokiniemi and
Kaisa Ryyn{\"{a}}nen and
Joni V{\"{a}}h{\"{a}} and
Elmo Kankkunen and
Kari Stadius and
Jussi Ryyn{\"{a}}nen},
title = {55-100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm {FDSOI} {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2186--2197},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3454350},
doi = {10.1109/TVLSI.2024.3454350},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JokiniemiRVKSR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoseKSTW24,
author = {Oliver Lexter July A. Jose and
Venkata Naveen Kolakaluri and
Ralph Gerard B. Sangalang and
Lean Karlo S. Tolentino and
Chua{-}Chin Wang},
title = {A 6.25-MHz 3.4-mW Single Clock {DPWM} Technique Using Matrix Shift
Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {972--976},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3367300},
doi = {10.1109/TVLSI.2024.3367300},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JoseKSTW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KangZXLWMP24,
author = {Ziyang Kang and
Jingwei Zhu and
Xun Xiao and
Shiming Li and
Lei Wang and
De Ma and
Gang Pan},
title = {LSM-Based Hotspot Prediction and Hotspot-Aware Routing in NoC-Based
Neuromorphic Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1239--1252},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3370850},
doi = {10.1109/TVLSI.2024.3370850},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KangZXLWMP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimNOR24,
author = {Sunwoong Kim and
Cameron James Norris and
James I. Oelund and
Rob A. Rutenbar},
title = {Area-Efficient Iterative Logarithmic Approximate Multipliers for {IEEE}
754 and Posit Numbers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {455--467},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3354726},
doi = {10.1109/TVLSI.2024.3354726},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimNOR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimZTSL24,
author = {Jinwoo Kim and
Lingjun Zhu and
Hakki Mert Torun and
Madhavan Swaminathan and
Sung Kyu Lim},
title = {A {PPA} Study for Heterogeneous 3-D {IC} Options: Monolithic, Hybrid
Bonding, and Microbumping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {401--412},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3342734},
doi = {10.1109/TVLSI.2023.3342734},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimZTSL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Kong24,
author = {Byeong Yong Kong},
title = {Low-Latency {PAPR} Reduction Architecture for Discrete Multitone Based
on Approximate Midrange},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2398--2402},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3430094},
doi = {10.1109/TVLSI.2024.3430094},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Kong24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LaiWZHLC24,
author = {Shin{-}Chi Lai and
Szu{-}Ting Wang and
Yi{-}Chang Zhu and
Ying{-}Hsiu Hung and
Jeng{-}Dao Lee and
Wei{-}Da Chen},
title = {High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform
Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral
Coefficients},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2139--2143},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3422994},
doi = {10.1109/TVLSI.2024.3422994},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LaiWZHLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LanL24,
author = {Yi{-}Hao Lan and
Shen{-}Iuan Liu},
title = {A 0.079-pJ/b/dB 32-Gb/s 2{\texttimes} Half-Baud-Rate {CDR} Circuit
With Frequency Detector},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {704--713},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3330012},
doi = {10.1109/TVLSI.2023.3330012},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LanL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LanL24a,
author = {Yi{-}Hao Lan and
Shen{-}Iuan Liu},
title = {A 36-Gb/s 2{\texttimes} Half-Baud-Rate Adaptive Receiver in 28-nm
{CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1263--1272},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3392680},
doi = {10.1109/TVLSI.2024.3392680},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LanL24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LaniusG24,
author = {Christian Lanius and
Tobias Gemmeke},
title = {Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory
Arrays for Genome Sequencing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {30--41},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3308262},
doi = {10.1109/TVLSI.2023.3308262},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LaniusG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLJKS24,
author = {Daehyeon Lee and
Junghee Lee and
Younggiu Jung and
Janghyuk Kauh and
Taigon Song},
title = {Robust Hardware Trojan Detection Method by Unsupervised Learning of
Electromagnetic Signals},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2327--2340},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3458892},
doi = {10.1109/TVLSI.2024.3458892},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLJKS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLK24,
author = {Hayoung Lee and
Sooryeong Lee and
Sungho Kang},
title = {RA-Aware Fail Data Collection Architecture for Cost Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1136--1149},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3343369},
doi = {10.1109/TVLSI.2023.3343369},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeePK24,
author = {Hayoung Lee and
Jongho Park and
Sungho Kang},
title = {An Area-Efficient Systolic Array Redundancy Architecture for Reliable
{AI} Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1950--1954},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3421563},
doi = {10.1109/TVLSI.2024.3421563},
timestamp = {Tue, 15 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeePK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeppanenLMJ24,
author = {Topi Lepp{\"{a}}nen and
Leevi Lepp{\"{a}}nen and
Joonas Multanen and
Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen},
title = {Bitstream Database-Driven {FPGA} Programming Flow Based on Standard
OpenCL},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2257--2268},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3458062},
doi = {10.1109/TVLSI.2024.3458062},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeppanenLMJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiC24,
author = {Hongge Li and
Yuhao Chen},
title = {Hybrid Stochastic Number and Its Neural Network Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {432--441},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3332170},
doi = {10.1109/TVLSI.2023.3332170},
timestamp = {Tue, 12 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCCJLZX24,
author = {Xiao Li and
Lin Chen and
Shixi Chen and
Fan Jiang and
Chengeng Li and
Wei Zhang and
Jiang Xu},
title = {Deep Reinforcement Learning-Based Power Management for Chiplet-Based
Multicore Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1726--1739},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3415487},
doi = {10.1109/TVLSI.2024.3415487},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCCJLZX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiFDSLZ24,
author = {Dengquan Li and
Tian Feng and
Jiale Ding and
Yi Shen and
Shubin Liu and
Zhangming Zhu},
title = {A Wideband Input Buffer Based on Cascade Complementary Source Follower},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {962--966},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3349564},
doi = {10.1109/TVLSI.2024.3349564},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiFDSLZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiGY24,
author = {Fan Li and
Yunqi Guan and
Wen Bin Ye},
title = {A Hardware and Software Co-Design for Energy-Efficient Neural Network
Accelerator With Multiplication-Less Folded-Accumulative {PE} for
Radar-Based Hand Gesture Recognition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1964--1968},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409674},
doi = {10.1109/TVLSI.2024.3409674},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiGY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiGYHZWZ24,
author = {Yao Li and
Junfeng Geng and
Mao Ye and
Jiaji He and
Xiaoxiao Zheng and
Qiuwei Wang and
Yiqiang Zhao},
title = {A {CMOS} Readout Circuit for Resistive Tactile Sensor Array Using
Crosstalk Suppression and Nonuniformity Compensation Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2368--2376},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3447164},
doi = {10.1109/TVLSI.2024.3447164},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiGYHZWZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiSYNGZY24,
author = {Chao Li and
Chen Sun and
Jianyi Yang and
Kai Ni and
Xiao Gong and
Cheng Zhuo and
Xunzhao Yin},
title = {Multibit Content Addressable Memory Design and Optimization Based
on 3-D nand-Compatible {IGZO} Flash},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1380--1388},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3392159},
doi = {10.1109/TVLSI.2024.3392159},
timestamp = {Mon, 25 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiSYNGZY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiSZ24,
author = {Enlai Li and
Sharad Sinha and
Wei Zhang},
title = {Unveiling the Advantages of Full Coherency Architecture for FPSoC
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1549--1553},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3368189},
doi = {10.1109/TVLSI.2024.3368189},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiSZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiVKL24,
author = {Yuyang Li and
Vijay Shankaran Vivekanand and
Rajkumar Kubendran and
Inhee Lee},
title = {Dynamic Neural Fields Accelerator Design for a Millimeter-Scale Tracking
System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1940--1944},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3416725},
doi = {10.1109/TVLSI.2024.3416725},
timestamp = {Thu, 14 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiVKL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWCZUBMWPDW24,
author = {Dongrui Li and
Ming Ming Wong and
Yi Sheng Chong and
Jun Zhou and
Mohit Upadhyay and
Ananta Narayanan Balaji and
Aarthy Mani and
Weng{-}Fai Wong and
Li{-}Shiuan Peh and
Anh Tuan Do and
Bo Wang},
title = {1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers
for In-Network Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2085--2092},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409652},
doi = {10.1109/TVLSI.2024.3409652},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWCZUBMWPDW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWZSXCZL24,
author = {Zeju Li and
Qinfan Wang and
Zihan Zou and
Qiao Shen and
Na Xie and
Hao Cai and
Hao Zhang and
Bo Liu},
title = {Layer-Sensitive Neural Processing Architecture for Error-Tolerant
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {797--809},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3369648},
doi = {10.1109/TVLSI.2024.3369648},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWZSXCZL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiYWH24,
author = {Bin Li and
Yunfei Yan and
Yuanxin Wei and
Heru Han},
title = {Scalable and Parallel Optimization of the Number Theoretic Transform
Based on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {291--304},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3312423},
doi = {10.1109/TVLSI.2023.3312423},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiYWH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCCTL24,
author = {Jia{-}Zhao Lin and
Po{-}Ta Chen and
Hung{-}Yuan Chin and
Pei{-}Yun Tsai and
Sz{-}Yuan Lee},
title = {Design and Implementation of a Real-Time Imaging Processor for Spaceborne
Synthetic Aperture Radar With Configurability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {669--681},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3338476},
doi = {10.1109/TVLSI.2023.3338476},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCCTL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCY24,
author = {Yu{-}Cheng Lin and
Ren{-}Hao Chiou and
Chia{-}Hsiang Yang},
title = {A High-Throughput Constructive Interference Precoder for 16 {\texttimes}
{MU-MIMO} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1878--1888},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3423341},
doi = {10.1109/TVLSI.2024.3423341},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinLHS24,
author = {Ko{-}Hong Lin and
Ont{-}Derh Lin and
Shi{-}Yu Huang and
Duo Sheng},
title = {Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed {BISG}
and Aging Sensing in a Chiplet-Based Design Environment},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2210--2219},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3435059},
doi = {10.1109/TVLSI.2024.3435059},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinLHS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinLL24,
author = {Jhe{-}En Lin and
Yi{-}Hao Lan and
Shen{-}Iuan Liu},
title = {A 40-Gb/s {PAM-3} Receiver With Modified Summer-Merged Slicers and
{PRTS} Checker},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1512--1522},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3393896},
doi = {10.1109/TVLSI.2024.3393896},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinLL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinLZGCX24,
author = {Xian Lin and
Heming Liu and
Xin Zheng and
Huaien Gao and
Shuting Cai and
Xiaoming Xiong},
title = {FPUx: High-Performance Floating-Point Support for Cost-Constrained
{RISC-V} Cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1945--1949},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3399221},
doi = {10.1109/TVLSI.2024.3399221},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinLZGCX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuCCWL24,
author = {Jun Liu and
Songren Cheng and
Tian Chen and
Xi Wu and
Huaguo Liang},
title = {A Self-Biased Current Reference Source-Based Pre-Bond {TSV} Test Solution},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {774--781},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3344272},
doi = {10.1109/TVLSI.2023.3344272},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuCCWL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuCSSFPWSKZWY24,
author = {Wenrui Liu and
Jiafeng Cheng and
Nengyuan Sun and
Heng Sha and
Zunxian Fu and
Zhaokang Peng and
Chunyang Wang and
Caiban Sun and
Pengliang Kong and
Yunfeng Zhao and
Yaoqiang Wang and
Weize Yu},
title = {A 128-Gbps Pipelined {SM4} Circuit With Dual {DPA} Attack Countermeasures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1164--1168},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3379205},
doi = {10.1109/TVLSI.2024.3379205},
timestamp = {Tue, 19 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuCSSFPWSKZWY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuKMS24,
author = {Si{-}Huang Liu and
Chia{-}Yi Kuo and
Yannan Mo and
Tao Su},
title = {An Area-Efficient, Conflict-Free, and Configurable Architecture for
Accelerating {NTT/INTT}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {519--529},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3336951},
doi = {10.1109/TVLSI.2023.3336951},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuKMS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuMJWZLZLC24,
author = {Shiwei Liu and
Chen Mu and
Hao Jiang and
Yunzhengmao Wang and
Jinshan Zhang and
Feng Lin and
Keji Zhou and
Qi Liu and
Chixiao Chen},
title = {{HARDSEA:} Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory
Computing Accelerator for Dynamic Sparse Self-Attention in Transformer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {269--282},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3337777},
doi = {10.1109/TVLSI.2023.3337777},
timestamp = {Fri, 02 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuMJWZLZLC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuWDXZ24,
author = {Yi{-}Fan Liu and
Dawei Wang and
Zhekang Dong and
Hao Xie and
Wen{-}Sheng Zhao},
title = {Implementation of Multiple-Step Quantized {STDP} Based on Novel Memristive
Synapses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1369--1379},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3393923},
doi = {10.1109/TVLSI.2024.3393923},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuWDXZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuYXWFLLGXS24,
author = {Feiran Liu and
Anran Yin and
Chen Xue and
Bo Wang and
Zhongyuan Feng and
Han Liu and
Xiang Li and
Hui Gao and
Tianzhu Xiong and
Xin Si},
title = {A 22-nm 264-GOPS/mm\({}^{\mbox{2}}\) 6T {SRAM} and Proportional Current
Compute Cell-Based Computing-in-Memory Macro for CNNs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2389--2393},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3446045},
doi = {10.1109/TVLSI.2024.3446045},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuYXWFLLGXS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuZWYZS24,
author = {Yiting Liu and
Hai Zhou and
Jia Wang and
Fan Yang and
Xuan Zeng and
Li Shang},
title = {Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary
Conditions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {810--822},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3363666},
doi = {10.1109/TVLSI.2024.3363666},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuZWYZS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LohG24,
author = {Johnson Loh and
Tobias Gemmeke},
title = {Stream Processing Architectures for Continuous {ECG} Monitoring Using
Subsampling- Based Classifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {68--78},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3329360},
doi = {10.1109/TVLSI.2023.3329360},
timestamp = {Fri, 08 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LohG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuCLPDXWL24,
author = {Yu Lu and
Xiaowu Cai and
Jian Lu and
Longli Pan and
Jianying Dang and
Yafei Xie and
Xupeng Wang and
Bo Li},
title = {A nMOS-R Cross-Coupled Level Shifter With High dV/dt Noise Immunity
for 600-V High-Voltage Gate Driver {IC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {1993--2000},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3417385},
doi = {10.1109/TVLSI.2024.3417385},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuCLPDXWL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuWAYLZQ24,
author = {Zhaojun Lu and
Xueyan Wang and
Md Tanvir Arafin and
Haoxiang Yang and
Zhenglin Liu and
Jiliang Zhang and
Gang Qu},
title = {An RRAM-Based Computing-in-Memory Architecture and Its Application
in Accelerating Transformer Inference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {485--496},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3345651},
doi = {10.1109/TVLSI.2023.3345651},
timestamp = {Wed, 20 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuWAYLZQ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuWGJCL24,
author = {Shan Lu and
Danyu Wu and
Xuan Guo and
Hanbo Jia and
Yong Chen and
Xinyu Liu},
title = {A 28-nm Dual-Mode Explicit Class-F{\unicode{8322}}{\unicode{8323}}
{VCO} With Low-Loss {CM} Return Path Achieving 70-400-kHz 1/f{\({^3}\)}
{PN} Corner Over 4.9-7.3-GHz {TR}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1749--1753},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3414158},
doi = {10.1109/TVLSI.2024.3414158},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuWGJCL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuZPLYLPXZT24,
author = {Zhifei Lu and
Bowen Zhang and
Xizhu Peng and
Hang Liu and
Xiaolei Ye and
Yuzhuo Li and
Yutao Peng and
Yao Xiao and
Wei Zhang and
He Tang},
title = {A New Artificial Neural Network-Based Calibration Mechanism for ADCs:
{A} Time-Interleaved {ADC} Case Study},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1184--1194},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3390220},
doi = {10.1109/TVLSI.2024.3390220},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuZPLYLPXZT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LunnikiviHH24,
author = {Henri Lunnikivi and
Roni H{\"{a}}m{\"{a}}l{\"{a}}inen and
Timo D. H{\"{a}}m{\"{a}}l{\"{a}}inen},
title = {Keelhaul: Processor-Driven Chip Connectivity and Memory Map Metadata
Validator for Large Systems-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2269--2280},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3454431},
doi = {10.1109/TVLSI.2024.3454431},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LunnikiviHH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoLLCAY24,
author = {Yuan{-}Chun Luo and
Anni Lu and
Yandong Luo and
Sou{-}Chi Chang and
Uygar Avci and
Shimeng Yu},
title = {Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer
in TPU-Like Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1696--1703},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3412631},
doi = {10.1109/TVLSI.2024.3412631},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoLLCAY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoLSSGSLPSY24,
author = {Yuan{-}Chun Luo and
Anni Lu and
Janak Sharda and
Moritz Scherer and
Jorge Tom{\'{a}}s G{\'{o}}mez and
Syed Shakib Sarwar and
Ziyun Li and
Reid Frederick Pinkham and
Barbara De Salvo and
Shimeng Yu},
title = {Thermally Constrained Codesign of Heterogeneous 3-D Integration of
Compute-in-Memory, Digital {ML} Accelerator, and {RISC-V} Cores for
Mixed {ML} and Non-ML Workloads},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1718--1725},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3415481},
doi = {10.1109/TVLSI.2024.3415481},
timestamp = {Tue, 01 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoLSSGSLPSY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoLWTDZ24,
author = {Li Luo and
Bochang Li and
Lidan Wang and
Jinpei Tan and
Shukai Duan and
Chunxiang Zhu},
title = {Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for
In-Memory Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {835--847},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3370176},
doi = {10.1109/TVLSI.2024.3370176},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoLWTDZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaLX24,
author = {Bingbing Ma and
Wei Li and
Hongtao Xu},
title = {Analysis and Calibration of Bit Weights in {SAR} and Pipelined {SAR}
ADCs Based on Code Distribution},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {977--990},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3382254},
doi = {10.1109/TVLSI.2024.3382254},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaLX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaXWCLZL24,
author = {Xiaoning Ma and
Qinzhi Xu and
Chenghan Wang and
He Cao and
Jianyun Liu and
Daoqing Zhang and
Zhiqiang Li},
title = {An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous
Integration Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1769--1781},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3430498},
doi = {10.1109/TVLSI.2024.3430498},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaXWCLZL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MathewsAIBYH24,
author = {Pranav O. Mathews and
Praveen Raj Ayyappan and
Afolabi Ige and
Swagat Bhattacharyya and
Linhao Yang and
Jennifer O. Hasler},
title = {A 65 nm {CMOS} Analog Programmable Standard Cell Library for Mixed-Signal
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1830--1840},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3432916},
doi = {10.1109/TVLSI.2024.3432916},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MathewsAIBYH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MatsuiTTT24,
author = {Chihiro Matsui and
Kasidit Toprasertpong and
Shinichi Takagi and
Ken Takeuchi},
title = {FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory
Circuit Design for Neuromorphic Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {468--479},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3336379},
doi = {10.1109/TVLSI.2023.3336379},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MatsuiTTT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MazzolaRB24,
author = {Sergio Mazzola and
Samuel Riedel and
Luca Benini},
title = {Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory
Manycore Clusters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1602--1615},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3415486},
doi = {10.1109/TVLSI.2024.3415486},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MazzolaRB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MintoCS24,
author = {Sameen Minto and
Austin Cable and
Wala Saadeh},
title = {A 206 {\(\mu\)}W Vital Signs Monitoring System on Chip for Measuring
Five Vitals},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1652--1660},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3415469},
doi = {10.1109/TVLSI.2024.3415469},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MintoCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MitrovicF24,
author = {Ana Mitrovic and
Eby G. Friedman},
title = {Thermal Exploration of {RSFQ} Integrated Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {728--738},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3348452},
doi = {10.1109/TVLSI.2023.3348452},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MitrovicF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Mohanty24,
author = {Basant Kumar Mohanty},
title = {Memory-Efficient Multiplier-Less 2-D {DWT} Design Using Combined Convolution
and Lifting Schemes for Wireless Visual Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {695--703},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3367817},
doi = {10.1109/TVLSI.2024.3367817},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Mohanty24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoheyLSKRA24,
author = {Ahmed M. Mohey and
Jelin Leslin and
Gaurav Singh and
Marko Kosunen and
Jussi Ryyn{\"{a}}nen and
Martin Andraud},
title = {A 22-nm All-Digital Time-Domain Neural Network Accelerator for Precision
In-Sensor Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2220--2231},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3496090},
doi = {10.1109/TVLSI.2024.3496090},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoheyLSKRA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MowlaviGGS24,
author = {Siavash Mowlavi and
Stavros Giannakopoulos and
Alexander Grabowski and
Lars Svensson},
title = {A Review of {IC} Drivers for VCSELs in Datacom Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {42--54},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3326876},
doi = {10.1109/TVLSI.2023.3326876},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MowlaviGGS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MustafaK24,
author = {Yerzhan Mustafa and
Sel{\c{c}}uk K{\"{o}}se},
title = {Built-In Self-Test of {SFQ} Circuits Using Side-Channel Leakage Information},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1100--1109},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3385014},
doi = {10.1109/TVLSI.2024.3385014},
timestamp = {Thu, 04 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MustafaK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuttakiRKTF24,
author = {Md Rafid Muttaki and
Md Habibur Rahman and
Akshay Kulkarni and
Mark M. Tehranipoor and
Farimah Farahmandi},
title = {{FTC:} {A} Universal Framework for Fault-Injection Attack Detection
and Prevention},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1311--1324},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3384531},
doi = {10.1109/TVLSI.2024.3384531},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MuttakiRKTF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NahvyN24,
author = {Alireza Nahvy and
Zainalabedin Navabi},
title = {Pico-Programmable Neurons to Reduce Computations for Deep Neural Network
Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1216--1227},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3386698},
doi = {10.1109/TVLSI.2024.3386698},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NahvyN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NgCKCG24,
author = {Jun{-}Sheng Ng and
Juncheng Chen and
Nay Aung Kyaw and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Securing Against Side-Channel Attacks With Wide-Range In Situ Random
Voltage Dithering on Async-Logic {AES} Engine},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1959--1963},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409650},
doi = {10.1109/TVLSI.2024.3409650},
timestamp = {Tue, 15 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NgCKCG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NguyenBMP24,
author = {Duy{-}Thanh Nguyen and
Abhiroop Bhattacharjee and
Abhishek Moitra and
Priyadarshini Panda},
title = {MCAIMem: {A} Mixed {SRAM} and eDRAM Cell for Area and Energy-Efficient
On-Chip {AI} Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2023--2036},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3439231},
doi = {10.1109/TVLSI.2024.3439231},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NguyenBMP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NolteTJHSWH24,
author = {Lars Nolte and
Tim Twardzik and
Camille Jalier and
Zhigang Huang and
Jiyuan Shi and
Thomas Wild and
Andreas Herkersdorf},
title = {{HW-FUTEX:} Hardware-Assisted Futex Syscall},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {16--29},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3317926},
doi = {10.1109/TVLSI.2023.3317926},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NolteTJHSWH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NurmiAS24,
author = {Jari Nurmi and
Snorre Aunet and
Alireza Saberkari},
title = {Guest Editorial Selected Papers From {IEEE} Nordic Circuits and Systems
Conference (NorCAS) 2022},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {1--3},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3339268},
doi = {10.1109/TVLSI.2023.3339268},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NurmiAS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NurmiAS24a,
author = {Jari Nurmi and
Snorre Aunet and
Alireza Saberkari},
title = {Guest Editorial Selected Papers From {IEEE} Nordic Circuits and Systems
Conference (NorCAS) 2023},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2169--2172},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3493512},
doi = {10.1109/TVLSI.2024.3493512},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NurmiAS24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OrtegaTPBC24,
author = {Eduardo Ortega and
Jonti Talukdar and
Woohyun Paik and
Tyler K. Bletsch and
Krishnendu Chakrabarty},
title = {Rowhammer Vulnerability of DRAMs in 3-D Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {967--971},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3368044},
doi = {10.1109/TVLSI.2024.3368044},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/OrtegaTPBC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PeiML24,
author = {Likai Pei and
Xiaodong Meng and
Xing Li},
title = {A Novel Digital-Controlled Current-Mode Single-Inductor-Multiple-Output
Buck Converter With Individual Output Overload Protection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {957--961},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3343763},
doi = {10.1109/TVLSI.2023.3343763},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PeiML24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengL24,
author = {Hsi{-}Kai Peng and
Shen{-}Iuan Liu},
title = {A 12.93-16 Gb/s Reference-Less Baud-Rate {CDR} Circuit With One-Tap
{DFE} and Semirotational Frequency Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {787--791},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3336020},
doi = {10.1109/TVLSI.2023.3336020},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PengL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PentapatiL24,
author = {Sai Pentapati and
Sung Kyu Lim},
title = {Heterogeneous Monolithic 3-D {IC} Designs: Challenges, {EDA} Solutions,
and Power, Performance, Cost Tradeoffs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {413--421},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3347372},
doi = {10.1109/TVLSI.2023.3347372},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PentapatiL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz24,
author = {Irith Pomeranz},
title = {Testability Evaluation for Local Design Modifications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {195--199},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3321572},
doi = {10.1109/TVLSI.2023.3321572},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz24a,
author = {Irith Pomeranz},
title = {Bit-Complemented Test Data to Replace the Tail of a Fault Coverage
Curve},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {609--618},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3365355},
doi = {10.1109/TVLSI.2024.3365355},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzZ24,
author = {Irith Pomeranz and
Yervant Zorian},
title = {Functionally Possible Path Delay Faults With High Functional Switching
Activity},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2159--2163},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3425817},
doi = {10.1109/TVLSI.2024.3425817},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ProulxCMF24,
author = {Alexandre Proulx and
Jean{-}Yves Chouinard and
Amine Miled and
Paul Fortier},
title = {Analyzing the Vulnerabilities of External {SDRAM} on System-on-Chip
Field Programmable Gate Array Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1124--1135},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3360370},
doi = {10.1109/TVLSI.2024.3360370},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ProulxCMF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QianZMXZY24,
author = {Yu Qian and
Liang Zhao and
Fanzi Meng and
Xiapeng Xu and
Cheng Zhuo and
Xunzhao Yin},
title = {Enhancing ConvNets With ConvFIFO: {A} Crossbar {PIM} Architecture
Based on Kernel-Stationary First-In-First-Out Dataflow},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1640--1651},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409648},
doi = {10.1109/TVLSI.2024.3409648},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QianZMXZY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahmanB24,
author = {Md. Moshiur Rahman and
Swarup Bhunia},
title = {Practical Implementation of Robust State-Space Obfuscation for Hardware
{IP} Protection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {333--346},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3307027},
doi = {10.1109/TVLSI.2023.3307027},
timestamp = {Sun, 03 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RahmanB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RathorSSM24,
author = {Vijaypal Singh Rathor and
Munesh Singh and
Kshira Sagar Sahoo and
Saraju P. Mohanty},
title = {GateLock: Input-Dependent Key-Based Locked Gates for {SAT} Resistant
Logic Locking},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {361--371},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3340350},
doi = {10.1109/TVLSI.2023.3340350},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RathorSSM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RenaKP24,
author = {Rakesh Varma Rena and
Raviteja Kammari and
Vijay Shankar Pasupureddi},
title = {A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion
{RF} Front-End},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {552--563},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3342022},
doi = {10.1109/TVLSI.2023.3342022},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RenaKP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RezaeiARL24,
author = {Hossein Rezaei and
Elham Abbasi and
Nandana Rajatheva and
Matti Latva{-}aho},
title = {Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of
Multi-Kernel Polar Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2107--2120},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3436872},
doi = {10.1109/TVLSI.2024.3436872},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RezaeiARL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RochaBNDOYKMMRB24,
author = {Leandro Mateus Giacomini Rocha and
Refik Bilgic and
Mohamed Naeim and
Sudipta Das and
Herman Oprins and
Amirreza Yousefzadeh and
Mario Konijnenburg and
Dragomir Milojevic and
James Myers and
Julien Ryckaert and
Dwaipayan Biswas},
title = {Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2144--2148},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3421625},
doi = {10.1109/TVLSI.2024.3421625},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RochaBNDOYKMMRB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RusanenSPRA24,
author = {Jere Rusanen and
Negar Shabanzadeh and
Aarno P{\"{a}}rssinen and
Timo Rahkonen and
Janne P. Aikio},
title = {Improving a Ka-Band Integrated Balanced Power Amplifier Performance
by Compensating Quadrature Hybrid Mismatch Effects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2198--2209},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3475810},
doi = {10.1109/TVLSI.2024.3475810},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RusanenSPRA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaberiSGS24,
author = {Mehdi Saberi and
Hossein Yaghoobzadeh Shadmehri and
Mohammad Tavakkoli Ghouchani and
Alexandre Schmid},
title = {A High-Precision and High-Dynamic-Range Current-Mode {WTA} Circuit
for Low-Supply-Voltage Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1955--1958},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3436575},
doi = {10.1109/TVLSI.2024.3436575},
timestamp = {Tue, 15 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SaberiSGS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SakamotoFAYM24,
author = {Junichi Sakamoto and
Daisuke Fujimoto and
Riku Anzai and
Naoki Yoshida and
Tsutomu Matsumoto},
title = {High-Throughput Bilinear Pairing Processor for Server-Side {FPGA}
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1498--1511},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3402164},
doi = {10.1109/TVLSI.2024.3402164},
timestamp = {Mon, 09 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SakamotoFAYM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SalaBS24,
author = {Riccardo Della Sala and
Davide Bellizia and
Giuseppe Scotti},
title = {Unveiling the True Power of the Latched Ring Oscillator for a Unified
{PUF} and {TRNG} Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2403--2407},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3448503},
doi = {10.1109/TVLSI.2024.3448503},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SalaBS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Salem24,
author = {Loai G. Salem},
title = {Symmetric and Multiphase-Interleaved Ladder Bucks for {DC} Capacitors
Elimination},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1554--1558},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3392617},
doi = {10.1109/TVLSI.2024.3392617},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Salem24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Salem24a,
author = {Loai G. Salem},
title = {Analysis and Optimization of Sense-and-Set Piezoelectric Energy Harvesting
Interface Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1630--1639},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409668},
doi = {10.1109/TVLSI.2024.3409668},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Salem24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SamantarayER24,
author = {Aswini K. Samantaray and
Pranose J. Edavoor and
Amol D. Rahulkar},
title = {A Novel Design Approach and {VLSI} Architecture of Rationalized Bi-Orthogonal
Wavelet Filter Banks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {619--632},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3342122},
doi = {10.1109/TVLSI.2023.3342122},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SamantarayER24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchirmerBBPE24,
author = {Tobias Schirmer and
Simon Buhr and
Felix Burkhardt and
Florian Protze and
Frank Ellinger},
title = {A High-Speed Dynamic Element Matching Decoder With Integrated Background
Calibration Control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2074--2084},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3432640},
doi = {10.1109/TVLSI.2024.3432640},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SchirmerBBPE24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeveroDANG24,
author = {Lucas Compassi Severo and
Tailize C. De{-}Oliveira and
Paulo C{\'{e}}sar Comassetto de Aguirre and
Wilhelmus A. M. Van Noije and
Alessandro Gon{\c{c}}alves Girardi},
title = {Variable Conversion Approach for Design Optimization of Low-Voltage
Low-Pass Filters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {205--218},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3335877},
doi = {10.1109/TVLSI.2023.3335877},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeveroDANG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShabanzadehPR24,
author = {Negar Shabanzadeh and
Aarno P{\"{a}}rssinen and
Timo Rahkonen},
title = {A Study on Nonlinearity in Mixers Using a Time-Varying Volterra-Based
Distortion Contribution Analysis Tool},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2232--2242},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3474183},
doi = {10.1109/TVLSI.2024.3474183},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShabanzadehPR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShadangiDC24,
author = {Ashish Ranjan Shadangi and
Suvra Sekhar Das and
Indrajit Chakrabarti},
title = {Low-Complexity {VLSI} Architecture for {OTFS} Transceiver Under Multipath
Fading Channel},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1285--1296},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3384114},
doi = {10.1109/TVLSI.2024.3384114},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShadangiDC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenJC24,
author = {Haoyang Shen and
Deepu John and
Barry Cardiff},
title = {FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in
Wireless Time-Varying Channel Environments},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1173--1183},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3355316},
doi = {10.1109/TVLSI.2024.3355316},
timestamp = {Mon, 09 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenJC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiCMW24,
author = {Huihong Shi and
Xin Cheng and
Wendong Mao and
Zhongfeng Wang},
title = {P\({}^{\mbox{2}}\)-ViT: Power-of-Two Post-Training Quantization and
Acceleration for Fully Quantized Vision Transformer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1704--1717},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3422684},
doi = {10.1109/TVLSI.2024.3422684},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiCMW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShrivastavaB24,
author = {Anshaj Shrivastava and
Gaurab Banerjee},
title = {Analog Probe Module {(APM)} for Enhanced {IC} Observability: From
Concept to Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2355--2367},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3470342},
doi = {10.1109/TVLSI.2024.3470342},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShrivastavaB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShuvoZFT24,
author = {Amit Mazumder Shuvo and
Tao Zhang and
Farimah Farahmandi and
Mark M. Tehranipoor},
title = {{FLAT:} Layout-Aware and Security Property-Assisted Timing Fault-Injection
Attack Assessment},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1150--1163},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3378291},
doi = {10.1109/TVLSI.2024.3378291},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShuvoZFT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SiDHSYGL24,
author = {Xin Si and
Fangyuan Dong and
Shengnan He and
Yuhui Shi and
Anran Yin and
Hui Gao and
Xiang Li},
title = {A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro
With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2164--2168},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3418888},
doi = {10.1109/TVLSI.2024.3418888},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SiDHSYGL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghaSIPA24,
author = {Thockchom Birjit Singha and
Basa Sanjana and
Titu Mary Ignatius and
Roy Paily Palathinkal and
Shaik Rafi Ahamed},
title = {Improvement in Resilience of {AES} Design With Reconfigured {CFB}
Mode Against Power Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2149--2153},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3422501},
doi = {10.1109/TVLSI.2024.3422501},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghaSIPA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongG24,
author = {Xiaoyong Song and
Zhichuan Guo},
title = {An Implementation of Reconfigurable Match Table for FPGA-Based Programmable
Switches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2121--2134},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3436047},
doi = {10.1109/TVLSI.2024.3436047},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongJCCYJ24,
author = {Changmin Song and
Hoyong Jung and
KyoungSeop Chang and
Kwanglae Cho and
Seungyong Yoon and
Young{-}Chan Jang},
title = {A 24-Gb/s {MIPI} {C-/D-PHY} Receiver Bridge Chip With Phase Error
Calibration Supporting FPGA-Based Frame Grabber},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {714--727},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3364839},
doi = {10.1109/TVLSI.2024.3364839},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SongJCCYJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SpagnoloPVFCC24,
author = {Fanny Spagnolo and
Stefania Perri and
Massimo Vatalaro and
Fabio Frustaci and
Felice Crupi and
Pasquale Corsonello},
title = {Exploring the Usage of Fast Carry Chains to Implement Multistage Ring
Oscillators on FPGAs: Design and Characterization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1472--1484},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3395302},
doi = {10.1109/TVLSI.2024.3395302},
timestamp = {Mon, 09 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SpagnoloPVFCC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SpinaRCRP24,
author = {Nunzio Spina and
Marcello Raimondi and
Alessandro Castorina and
Egidio Ragonese and
Giuseppe Palmisano},
title = {A Three-Channel Package-Scale Galvanic Isolation Interface for Wide
Bandgap Gate Drivers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1389--1399},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3383606},
doi = {10.1109/TVLSI.2024.3383606},
timestamp = {Mon, 09 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SpinaRCRP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrivastavaDCPSPB24,
author = {Amisha Srivastava and
Sanjay Das and
Navnil Choudhury and
Rafail Psiakis and
Pedro Henrique Silva and
Debjit Pal and
Kanad Basu},
title = {{SCAR:} Power Side-Channel Analysis at {RTL} Level},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1110--1123},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3390601},
doi = {10.1109/TVLSI.2024.3390601},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SrivastavaDCPSPB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TacoGHTYL24,
author = {Ramiro Taco and
Esteban Garz{\'{o}}n and
Robert Hanhan and
Adam Teman and
Leonid Yavits and
Marco Lanuzza},
title = {Designing Precharge-Free Energy-Efficient Content-Addressable Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2303--2314},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3475036},
doi = {10.1109/TVLSI.2024.3475036},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TacoGHTYL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TalukdarPOC24,
author = {Jonti Talukdar and
Woohyun Paik and
Eduardo Ortega and
Krishnendu Chakrabarty},
title = {ALT-Lock: Logic and Timing Ambiguity-Based {IP} Obfuscation Against
Reverse Engineering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1535--1548},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3411033},
doi = {10.1109/TVLSI.2024.3411033},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TalukdarPOC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangGZSWFFZ24,
author = {Zijian Tang and
Yongxiang Guo and
Minqian Zheng and
Chao Sun and
Yusong Wu and
Runjiu Fang and
Ying Fang and
Milin Zhang},
title = {An 112-Ch Neural Signal Acquisition SoC With Full-Channel Read-Out
and Processing Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1461--1471},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3396774},
doi = {10.1109/TVLSI.2024.3396774},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TangGZSWFFZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TangZ24,
author = {Yok Jye Tang and
Xinmiao Zhang},
title = {Low-Complexity Parallel Chien Search Architecture Based on Vandermonde
Matrix Decomposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1744--1748},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3394396},
doi = {10.1109/TVLSI.2024.3394396},
timestamp = {Mon, 11 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TangZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TavakoliRQR24,
author = {Erfan Bank Tavakoli and
Michael Riera and
Masudul Hassan Quraishi and
Fengbo Ren},
title = {FSpGEMM: {A} Framework for Accelerating Sparse General Matrix-Matrix
Multiplication Using Gustavson's Algorithm on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {633--644},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3355499},
doi = {10.1109/TVLSI.2024.3355499},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TavakoliRQR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThirumoorthiLHMK24,
author = {Madhan Thirumoorthi and
Alexander J. Leigh and
Moslem Heidarpur and
Mitra Mirhassani and
Mohammed A. S. Khalid},
title = {A High Speed and Area Efficient Processor for Elliptic Curve Scalar
Point Multiplication for GF(2\({}^{\mbox{m}}\))},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1423--1435},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3394871},
doi = {10.1109/TVLSI.2024.3394871},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ThirumoorthiLHMK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TranDDHPH24,
author = {Thai{-}Ha Tran and
Duc{-}Thuan Dam and
Ba{-}Anh Dao and
Van{-}Phuc Hoang and
Cong{-}Kha Pham and
Trong{-}Thuc Hoang},
title = {Compacting Side-Channel Measurements With Amplitude Peak Location
Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {573--586},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3339810},
doi = {10.1109/TVLSI.2023.3339810},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TranDDHPH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TranDLHHP24,
author = {Thai{-}Ha Tran and
Ba{-}Anh Dao and
Duc{-}Hung Le and
Van{-}Phuc Hoang and
Trong{-}Thuc Hoang and
Cong{-}Kha Pham},
title = {Spread Spectrum-Based Countermeasures for Cryptographic {RISC-V} SoC},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2341--2354},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3444851},
doi = {10.1109/TVLSI.2024.3444851},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TranDLHHP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UsamiYKASHB24,
author = {Kimiyoshi Usami and
Daiki Yokoyama and
Aika Kamei and
Hideharu Amano and
Kenta Suzuki and
Keizo Hiraga and
Kazuhiro Bessho},
title = {Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops
to Minimize Store Energy Under Process and Temperature Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {89--102},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3318468},
doi = {10.1109/TVLSI.2023.3318468},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/UsamiYKASHB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VafaeiA24,
author = {Jafar Vafaei and
Omid Akbari},
title = {HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier
by Approximate Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2012--2022},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3445108},
doi = {10.1109/TVLSI.2024.3445108},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VafaeiA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VafaieenezhadG24,
author = {M. Vafaieenezhad and
M. B. Ghaznavi{-}Ghoushchi},
title = {An Unconditional Evenly Spaced {STRO} With a New Mitigated Drafting
Effect Muller C-Element},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1564--1568},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3393989},
doi = {10.1109/TVLSI.2024.3393989},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VafaieenezhadG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VasanthiRR24,
author = {D. R. Vasanthi and
Sanampudi Gopala Krishna Reddy and
Madhav Rao},
title = {{HRM:} M-Term Heterogeneous Hybrid Blend Recursive Multiplier for
GF(2\({}^{\mbox{n}}\)) Polynomial},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1447--1460},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3393860},
doi = {10.1109/TVLSI.2024.3393860},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VasanthiRR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VegaSB24,
author = {Christopher Vega and
Patanjali SLPSK and
Swarup Bhunia},
title = {IOLock: An Input/Output Locking Scheme for Protection Against Reverse
Engineering Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {347--360},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3337310},
doi = {10.1109/TVLSI.2023.3337310},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VegaSB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangXNCLZL24,
author = {Chenghan Wang and
Qinzhi Xu and
Chuanjun Nie and
He Cao and
Jianyun Liu and
Daoqing Zhang and
Zhiqiang Li},
title = {A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration
System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {178--189},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3321933},
doi = {10.1109/TVLSI.2023.3321933},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangXNCLZL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZLS24,
author = {Xingyu Wang and
Ruilin Zhang and
Kunyang Liu and
Hirofumi Shinohara},
title = {A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring
Static Inverter Selection and Noise Enhancement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {564--572},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3328602},
doi = {10.1109/TVLSI.2023.3328602},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZLS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZOYFCCJW24,
author = {Zilin Wang and
Yi Zhong and
Zehong Ou and
Youming Yang and
Shuo Feng and
Guang Chen and
Xiaoxin Cui and
Song Jia and
Yuan Wang},
title = {Marmotini: {A} Weight Density Adaptation Architecture With Hybrid
Compression Method for Spiking Neural Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2293--2302},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3453897},
doi = {10.1109/TVLSI.2024.3453897},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZOYFCCJW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WijayaCPBK24,
author = {Joshua Adiel Wijaya and
Poki Chen and
Lucky Kumar Pradhan and
Ahmad Shahid Bhatti and
Seiji Kajihara},
title = {Area Efficient 0.009-mm\({}^{\mbox{2}}\) 28.1-ppm/{\textdegree}C 11.3-MHz
{ALL-MOS} Relaxation Oscillator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1900--1907},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3416992},
doi = {10.1109/TVLSI.2024.3416992},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WijayaCPBK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuWLW24,
author = {Xiao Wu and
Miaoxin Wang and
Jun Lin and
Zhongfeng Wang},
title = {Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel
CNNs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1086--1099},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3383871},
doi = {10.1109/TVLSI.2024.3383871},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WuWLW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuWZC24,
author = {Le Wu and
Liji Wu and
Xiangmin Zhang and
Munkhbaatar Chinbat},
title = {Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for {DNN}
Systolic Array},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1740--1743},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3387986},
doi = {10.1109/TVLSI.2024.3387986},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WuWZC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuZZLCLZC24,
author = {Lizhou Wu and
Haozhe Zhu and
Jiapei Zheng and
Mengjie Li and
Yinuo Cheng and
Qi Liu and
Xiaoyang Zeng and
Chixiao Chen},
title = {Hi-NeRF: {A} Multicore NeRF Accelerator With Hierarchical Empty Space
Skipping for Edge 3-D Rendering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {12},
pages = {2315--2326},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3458032},
doi = {10.1109/TVLSI.2024.3458032},
timestamp = {Wed, 08 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuZZLCLZC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaWCGF24,
author = {Bowen Xia and
De{-}han Wang and
Wenhua Chen and
Fadhel M. Ghannouchi and
Zhenghe Feng},
title = {A 24-40-GHz Broadband Beamforming {TRX} Front-End {IC} With Unified
Phase and Gain Control for Multiband Phased Array Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1297--1310},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3395546},
doi = {10.1109/TVLSI.2024.3395546},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaWCGF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieSCDD24,
author = {Chenjia Xie and
Zhuang Shao and
Zhichao Chen and
Yuan Du and
Li Du},
title = {An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal
Redundancy Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {4},
pages = {782--786},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3335232},
doi = {10.1109/TVLSI.2023.3335232},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XieSCDD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiongCLWLH24,
author = {Wei Xiong and
Jiacheng Cao and
Yaozhang Liu and
Jian Wang and
Jinmei Lai and
Miaoqing Huang},
title = {A Reliable and Efficient Online Solution for Adaptive Voltage and
Frequency Scaling on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1058--1071},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3361459},
doi = {10.1109/TVLSI.2024.3361459},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiongCLWLH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuLFLL24,
author = {Chengzhi Xu and
Xufeng Liao and
Peiyuan Fu and
Yongyuan Li and
Lianxi Liu},
title = {A Dual-Mode Buck Converter with Light-Load Efficiency Improvement
and Seamless Mode Transition Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1782--1791},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3422382},
doi = {10.1109/TVLSI.2024.3422382},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuLFLL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuWHWCL24,
author = {Dongdong Xu and
Xiang Wang and
Qiang Hao and
Jiqing Wang and
Shuangjie Cui and
Bo Liu},
title = {A High-Performance Transparent Memory Data Encryption and Authentication
Scheme Based on Ascon Cipher},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {925--937},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3372026},
doi = {10.1109/TVLSI.2024.3372026},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuWHWCL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuWOS24,
author = {Yichen Xu and
Zhaoqing Wang and
Jonghyun Oh and
Mingoo Seok},
title = {Model-Based Study on the Limit of the Dynamic Load Regulation Performance
of a Digital Low Dropout Regulator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1822--1829},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3425771},
doi = {10.1109/TVLSI.2024.3425771},
timestamp = {Tue, 15 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuWOS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuanRXWL24,
author = {Zhuo Xuan and
Shiwei Ren and
Chengbo Xue and
Guiyu Wang and
Xiangnan Li},
title = {A Hardware Acceleration of Maximum Likelihood Estimation Algorithm
With Alternating Projection on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1072--1085},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3366206},
doi = {10.1109/TVLSI.2024.3366206},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuanRXWL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanQZHMC24,
author = {Xiang Yan and
Kefan Qin and
Xinyue Zheng and
Weibo Hu and
Wei Ma and
Haitao Cui},
title = {A Two-Channel Interleaved {ADC} With Fast-Converging Foreground Time
Calibration and Comparison-Based Control Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2001--2011},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3449293},
doi = {10.1109/TVLSI.2024.3449293},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanQZHMC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanSGLWXSWH24,
author = {Run Yan and
Yin Su and
Hui Guo and
Yashuai L{\"{u}} and
Jin Wang and
Nong Xiao and
Li Shen and
Yongwen Wang and
Libo Huang},
title = {{MPRTA:} An Efficient Multilevel Parallel Mobile Accelerator for High-Performance
Ray Tracing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {396--400},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3334711},
doi = {10.1109/TVLSI.2023.3334711},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanSGLWXSWH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanWCHNGW24,
author = {Aibin Yan and
Litao Wang and
Jie Cui and
Zhengfeng Huang and
Tianming Ni and
Patrick Girard and
Xiaoqing Wen},
title = {Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using
Magnetic Tunnel Junctions and {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {116--127},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3323562},
doi = {10.1109/TVLSI.2023.3323562},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanWCHNGW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanZLCG24,
author = {Xu Yan and
Jingyuan Zhang and
Guansheng Lv and
Wenhua Chen and
Yongxin Guo},
title = {Gain and Power Enhancement With Coupled Technique for a Distributed
Power Amplifier in 0.25- {\(\mu\)}m GaN {HEMT} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1523--1534},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3411143},
doi = {10.1109/TVLSI.2024.3411143},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YanZLCG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangMXXWM24,
author = {Chen Yang and
Yishuo Meng and
Jiawei Xi and
Siwei Xiang and
Jianfei Wang and
Kuizhi Mei},
title = {{WRA-SS:} {A} High-Performance Accelerator Integrating Winograd With
Structured Sparsity for Convolutional Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {1},
pages = {164--177},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3330993},
doi = {10.1109/TVLSI.2023.3330993},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangMXXWM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YouseflooA24,
author = {Morteza Yousefloo and
Omid Akbari},
title = {Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit
Number Representation System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {7},
pages = {1350--1363},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3396555},
doi = {10.1109/TVLSI.2024.3396555},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YouseflooA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuLDWJZL24,
author = {Runze Yu and
Zhenhao Li and
Xi Deng and
Zhaoxu Wang and
Wei Jia and
Haoming Zhang and
Zhenglin Liu},
title = {iEDCL: Streamlined, False-Error-Free Error Detection and Correction
Scheme in a Near-Threshold Enabled 32-bit Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1436--1446},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409315},
doi = {10.1109/TVLSI.2024.3409315},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuLDWJZL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuPLGBAAC24,
author = {Pengbo Yu and
Flavio Ponzina and
Alexandre Levisse and
Mohit Gupta and
Dwaipayan Biswas and
Giovanni Ansaloni and
David Atienza and
Francky Catthoor},
title = {An Energy Efficient Soft {SIMD} Microarchitecture and Its Application
on Quantized CNNs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1018--1031},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3375793},
doi = {10.1109/TVLSI.2024.3375793},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuPLGBAAC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuWCYL24,
author = {Tianyang Yu and
Bi Wu and
Ke Chen and
Chenggang Yan and
Weiqiang Liu},
title = {Toward Efficient Retraining: {A} Large-Scale Approximate Neural Network
Framework With Cross-Layer Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1004--1017},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3386900},
doi = {10.1109/TVLSI.2024.3386900},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuWCYL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZareieEEF24,
author = {Mahsa Zareie and
Kamal El{-}Sankary and
Ezz I. El{-}Masry and
Ximing Fu},
title = {An Open-Loop {VCO-ADC} Based on a Linearized Current Control Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {587--591},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3337205},
doi = {10.1109/TVLSI.2023.3337205},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZareieEEF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangCMJLW24,
author = {Jingqi Zhang and
Zhiming Chen and
Mingzhi Ma and
Rongkun Jiang and
Hongshuo Li and
Weijiang Wang},
title = {High-Performance {ECC} Scalar Multiplication Architecture Based on
Comb Method and Low-Latency Window Recoding Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {382--395},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3321772},
doi = {10.1109/TVLSI.2023.3321772},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangCMJLW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangCP24,
author = {Bo Zhang and
Zeming Cheng and
Massoud Pedram},
title = {Design of a High-Performance Iterative Barrett Modular Multiplier
for Crypto Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {897--910},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3368002},
doi = {10.1109/TVLSI.2024.3368002},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangCP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangLI24,
author = {Haoming Zhang and
Shuowei Li and
Tetsuya Iizuka},
title = {A Single Ring-Oscillator-Based Test Structure for Timing Characterization
of Dynamic Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {938--951},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3370862},
doi = {10.1109/TVLSI.2024.3370862},
timestamp = {Sat, 08 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangLI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangQHX24,
author = {Yongqiang Zhang and
Jiao Qin and
Jie Han and
Guangjun Xie},
title = {Design of a Stochastic Computing Architecture for the Phansalkar Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {442--454},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3348809},
doi = {10.1109/TVLSI.2023.3348809},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangQHX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangRKAF24,
author = {Tao Zhang and
Md Latifur Rahman and
Hadi Mardani Kamali and
Kimia Zamiri Azar and
Farimah Farahmandi},
title = {SiPGuard: Run-Time System-in-Package Security Monitoring via Power
Noise Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {305--318},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3322384},
doi = {10.1109/TVLSI.2023.3322384},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangRKAF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangTF24,
author = {Tao Zhang and
Mark M. Tehranipoor and
Farimah Farahmandi},
title = {TrustGuard: Standalone FPGA-Based Security Monitoring Through Power
Side-Channel},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {2},
pages = {319--332},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3335876},
doi = {10.1109/TVLSI.2023.3335876},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangTF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangTJLL24,
author = {Youming Zhang and
Xusheng Tang and
Tonglu Jiao and
Peng Liu and
Jingchen Liu},
title = {Design of Octave Tuning Range {LC} {VCO} With Ultralow K\({}_{\mbox{VCO}}\)
Using Frequency-Dependent Implicit Capacitance Neutralization Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1908--1918},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3430544},
doi = {10.1109/TVLSI.2024.3430544},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangTJLL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangTZTL24,
author = {Yichen Zhang and
Chaowei Tang and
Yanqi Zheng and
Xian Tang and
Ka Nang Leung},
title = {An Adaptive Zero-Current Detector for Single-Inductor Multiple-Output
{DC-DC} Converter With Full-Wave Current Sensor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {9},
pages = {1764--1768},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3415475},
doi = {10.1109/TVLSI.2024.3415475},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangTZTL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWYLXXLH24,
author = {Jinming Zhang and
Xuyan Wang and
Yaoyao Ye and
Dongxu Lyu and
Guojie Xiong and
Ningyi Xu and
Yong Lian and
Guanghui He},
title = {{M2M:} {A} Fine-Grained Mapping Framework to Accelerate Multiple DNNs
on a Multi-Chiplet Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1864--1877},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3438549},
doi = {10.1109/TVLSI.2024.3438549},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWYLXXLH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangYHDD24,
author = {Heng Zhang and
Wenhe Yin and
Sunan He and
Yuan Du and
Li Du},
title = {An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating
Transformer Feed-Forward Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1889--1899},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3432403},
doi = {10.1109/TVLSI.2024.3432403},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangYHDD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengCCGXC24,
author = {Xin Zheng and
Mingjun Cheng and
Jiasong Chen and
Huaien Gao and
Xiaoming Xiong and
Shuting Cai},
title = {{BSSE:} Design Space Exploration on the {BOOM} With Semi-Supervised
Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {5},
pages = {860--869},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3368075},
doi = {10.1109/TVLSI.2024.3368075},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengCCGXC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengLDYSZSQZLWZ24,
author = {Yifei Zheng and
Boyu Li and
Qianheng Dong and
Yutao Ying and
Deyuan Song and
Jing Zhu and
Weifeng Sun and
Qinsong Qian and
Long Zhang and
Sheng Li and
Denggui Wang and
Jianjun Zhou},
title = {A 200-V Half-Bridge Monolithic GaN Power {IC} With High-Speed Level
Shifter and dV\({}_{\mbox{S}}\)/dt Noise Immunity Enhancement Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {542--551},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2023.3335137},
doi = {10.1109/TVLSI.2023.3335137},
timestamp = {Sun, 08 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengLDYSZSQZLWZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengYLLWZ24,
author = {Xiaoxiao Zheng and
Mao Ye and
Zhiwei Li and
Yao Li and
Qiuwei Wang and
Yiqiang Zhao},
title = {A {CMOS} {AFE} Array With {DC} Input Current Cancellation for {FMCW}
LiDAR},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {3},
pages = {422--431},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3350870},
doi = {10.1109/TVLSI.2024.3350870},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengYLLWZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouDH24,
author = {Zikang Zhou and
Xuyang Duan and
Jun Han},
title = {A Design Framework for Generating Energy-Efficient Accelerator on
{FPGA} Toward Low-Level Vision},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {8},
pages = {1485--1497},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3409649},
doi = {10.1109/TVLSI.2024.3409649},
timestamp = {Thu, 22 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouDH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouT24,
author = {Ziliang Zhou and
Min Tan},
title = {A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion
Loss and Overstress in 65-nm Standard {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1812--1821},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3435974},
doi = {10.1109/TVLSI.2024.3435974},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouWZZSZXLMZW24,
author = {Yang Zhou and
Wenjie Wang and
Longbin Zhu and
Zhengtao Zhu and
Risheng Su and
Jianan Zheng and
Siyuan Xie and
Jihong Li and
Fanyi Meng and
Zhijun Zhou and
Keping Wang},
title = {A Second-Order Noise Shaping {SAR} {ADC} With Parallel Multiresidual
Integrator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {11},
pages = {2135--2138},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3447740},
doi = {10.1109/TVLSI.2024.3447740},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouWZZSZXLMZW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouXWWXWY24,
author = {Lingfeng Zhou and
Shanlin Xiao and
Huiyao Wang and
Jinghai Wang and
Zeyang Xu and
Bohan Wang and
Zhiyi Yu},
title = {Better-Than-Worst-Case: {A} Frequency Adaptation Asynchronous {RISC-V}
Core With Vector Extension},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {6},
pages = {1045--1057},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3375350},
doi = {10.1109/TVLSI.2024.3375350},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouXWWXWY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouXWWXWY24a,
author = {Lingfeng Zhou and
Shanlin Xiao and
Huiyao Wang and
Jinghai Wang and
Zeyang Xu and
Bohan Wang and
Zhiyi Yu},
title = {Toward Efficient Asynchronous Circuits Design Flow Using Backward
Delay Propagation Constraint},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1852--1863},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3418769},
doi = {10.1109/TVLSI.2024.3418769},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouXWWXWY24a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuZ24,
author = {Yankun Zhu and
Pingqiang Zhou},
title = {Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring
Simple but Effective Clocking Methodologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {32},
number = {10},
pages = {1919--1929},
year = {2024},
url = {https://doi.org/10.1109/TVLSI.2024.3418961},
doi = {10.1109/TVLSI.2024.3418961},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0001NM23,
author = {Chandan Kumar Jha and
Ankita Nandi and
Joycee Mekie},
title = {Single Exact Single Approximate Adders and Single Exact Dual Approximate
Adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {907--916},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3268275},
doi = {10.1109/TVLSI.2023.3268275},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/0001NM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0001SGB23,
author = {Jonathan Cruz and
Patanjali SLPSK and
Pravin Gaikwad and
Swarup Bhunia},
title = {{TVF:} {A} Metric for Quantifying Vulnerability Against Hardware Trojan
Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {969--979},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3270866},
doi = {10.1109/TVLSI.2023.3270866},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/0001SGB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0005MYE23,
author = {Tao Li and
Yitao Ma and
Ko Yoshikawa and
Tetsuo Endoh},
title = {Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer
Multiplier for Energy-Efficient STT-MRAM-Based {AI} Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1078--1082},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3245099},
doi = {10.1109/TVLSI.2023.3245099},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/0005MYE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbbasJC23,
author = {Abdullah Ibn Abbas and
Xiangdong Jia and
Glenn E. R. Cowan},
title = {A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver
Front-End for Energy-Efficient Dual-Rate Optical Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {431--441},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3238286},
doi = {10.1109/TVLSI.2023.3238286},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AbbasJC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbbasJG23,
author = {Syed Mohsin Abbas and
Marwan Jalaleddine and
Warren J. Gross},
title = {List-GRAND: {A} Practical Way to Achieve Maximum Likelihood Decoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {43--54},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3223692},
doi = {10.1109/TVLSI.2022.3223692},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbbasJG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AdionoRSSML23,
author = {Trio Adiono and
Rhesa Muhammad Ramadhan and
Nana Sutisna and
Infall Syafalni and
Rahmat Mulyawan and
Chang Hong Lin},
title = {Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary
Systolic Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1774--1787},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3305937},
doi = {10.1109/TVLSI.2023.3305937},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AdionoRSSML23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AkbariHHKKT23,
author = {Meysam Akbari and
Safwan Mawlood Hussein and
Yasir Hashim and
Fabian Khateb and
Tomasz Kulej and
Kea{-}Tiong Tang},
title = {Implementation of a Multipath Fully Differential {OTA} in 0.18-{\(\mu\)}m
{CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {147--151},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3218741},
doi = {10.1109/TVLSI.2022.3218741},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AkbariHHKKT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AkbariHHKT23,
author = {Meysam Akbari and
Safwan Mawlood Hussein and
Yasir Hashim and
Fabian Khateb and
Kea{-}Tiong Tang},
title = {A Rail-to-Rail Transconductance Amplifier Based on Current Generator
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1624--1628},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3285823},
doi = {10.1109/TVLSI.2023.3285823},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AkbariHHKT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AksoyNARFDP23,
author = {Levent Aksoy and
Quang{-}Linh Nguyen and
Felipe Almeida and
Jaan Raik and
Marie{-}Lise Flottes and
Sophie Dupuis and
Samuel Pagliarini},
title = {Hybrid Protection of Digital {FIR} Filters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {812--825},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3253641},
doi = {10.1109/TVLSI.2023.3253641},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AksoyNARFDP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlacchiGGKG23,
author = {Aur{\'{e}}lien Alacchi and
Edouard Giacomin and
Roman Gauchi and
Szymon Kulis and
Pierre{-}Emmanuel Gaillardon},
title = {Smart-Redundancy With In Memory {ECC} Checking: Low-Power SEE-Resistant
{FPGA} Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1204--1213},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3279228},
doi = {10.1109/TVLSI.2023.3279228},
timestamp = {Sun, 06 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AlacchiGGKG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto23,
author = {Massimo Alioto},
title = {Opening of the 2023 Editorial Year - This Coda as Prelude of Next
{TVLSI} Cycle With Sustained Growth},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {1--3},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3228023},
doi = {10.1109/TVLSI.2022.3228023},
timestamp = {Mon, 02 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AminzadehBGVJ23,
author = {Hamed Aminzadeh and
Andrea Ballo and
Alfio Dario Grasso and
Mohammad Mahdi Valinezhad and
Mohammad Jamali},
title = {Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving
a Wide Range of C\({}_{\mbox{L}}\)},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1665--1674},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3313613},
doi = {10.1109/TVLSI.2023.3313613},
timestamp = {Wed, 01 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AminzadehBGVJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzadYAPTJ23,
author = {Zahra Azad and
Guowei Yang and
Rashmi Agrawal and
Daniel Petrisko and
Michael Bedford Taylor and
Ajay Joshi},
title = {{RISE:} {RISC-V} SoC for En/Decryption Acceleration on the Edge for
Homomorphic Encryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1523--1536},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3288754},
doi = {10.1109/TVLSI.2023.3288754},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AzadYAPTJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BadriSG23,
author = {SatyaJaswanth Badri and
Mukesh Saini and
Neeraj Goel},
title = {An Efficient NVM-Based Architecture for Intermittent Computing Under
Energy Constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {725--737},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3266555},
doi = {10.1109/TVLSI.2023.3266555},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BadriSG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaeLYS23,
author = {Seongun Bae and
Minseob Lee and
Sang{-}Min Yoo and
Jae{-}Yoon Sim},
title = {A Temperature Compensated Ring Oscillator With LC-Based Period Error
Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2152--2156},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3322709},
doi = {10.1109/TVLSI.2023.3322709},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaeLYS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaeOLL23,
author = {Junyeong Bae and
Junseok Oh and
Myoung Jin Lee and
Young{-}Woo Lee},
title = {Timestamp-Based Secure Shield Architecture for Detecting Invasive
Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1358--1367},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3297616},
doi = {10.1109/TVLSI.2023.3297616},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaeOLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaiWJGYWLRS23,
author = {Fujun Bai and
Song Wang and
Xuerong Jia and
Yixin Guo and
Bing Yu and
Hang Wang and
Cong Lai and
Qiwei Ren and
Hongbin Sun},
title = {A Low-Cost Reduced-Latency {DRAM} Architecture With Dynamic Reconfiguration
of Row Decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {128--141},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3219437},
doi = {10.1109/TVLSI.2022.3219437},
timestamp = {Sun, 30 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaiWJGYWLRS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalloGPS23,
author = {Andrea Ballo and
Alfio Dario Grasso and
Salvatore Pennisi and
Giovanni Susinni},
title = {A 0.3-V 8.5-{\(\mu\)} a Bulk-Driven {OTA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1444--1448},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3266806},
doi = {10.1109/TVLSI.2023.3266806},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BalloGPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BathlaV23,
author = {Shivani Bathla and
Vinita Vasudevan},
title = {A Framework for Reliability Analysis of Combinational Circuits Using
Approximate Bayesian Inference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {543--554},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3237885},
doi = {10.1109/TVLSI.2023.3237885},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BathlaV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhandariMTPGTTGK23,
author = {Jitendra Bhandari and
Abdul Khader Thalakkattu Moosa and
Benjamin Tan and
Christian Pilato and
Ganesh Gore and
Xifan Tang and
Scott Temple and
Pierre{-}Emmanuel Gaillardon and
Ramesh Karri},
title = {Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for
{IP} Redaction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1459--1471},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3301334},
doi = {10.1109/TVLSI.2023.3301334},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BhandariMTPGTTGK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BiccarioVND23,
author = {Giuseppe E. Biccario and
Oleg Vitrenko and
Roberto Nonis and
Stefano D'Amico},
title = {A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm
{CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {636--643},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3240002},
doi = {10.1109/TVLSI.2023.3240002},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BiccarioVND23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BrennsteinerATM23,
author = {Stefan Brennsteiner and
Tughrul Arslan and
John S. Thompson and
Andrew C. McCormick},
title = {LAMANet: {A} Real-Time, Machine Learning-Enhanced Approximate Message
Passing Detector for Massive {MIMO}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {382--395},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3225505},
doi = {10.1109/TVLSI.2022.3225505},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BrennsteinerATM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BundFM23,
author = {Johannes Bund and
Matthias F{\"{u}}gger and
Moti Medina},
title = {{PALS:} Distributed Gradient Clocking on Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1740--1753},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3311178},
doi = {10.1109/TVLSI.2023.3311178},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BundFM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CantoKA23,
author = {Alvaro Cintas Canto and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Reliable Architectures for Finite Field Multipliers Using Cyclic Codes
on {FPGA} Utilized in Classic and Post-Quantum Cryptography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {157--161},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224357},
doi = {10.1109/TVLSI.2022.3224357},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CantoKA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoHDZWY23,
author = {Peng Cao and
Guoqing He and
Wenjie Ding and
Zhanhua Zhang and
Kai Wang and
Jun Yang},
title = {Efficient and Accurate {ECO} Leakage Optimization Framework With {GNN}
and Bidirectional {LSTM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1413--1424},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3283256},
doi = {10.1109/TVLSI.2023.3283256},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoHDZWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaudhuriBKLC23,
author = {Arjun Chaudhuri and
Sanmitra Banerjee and
Jinwoo Kim and
Sung Kyu Lim and
Krishnendu Chakrabarty},
title = {Built-In Self-Test of High-Density and Realistic {ILV} Layouts in
Monolithic 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {296--309},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3228850},
doi = {10.1109/TVLSI.2022.3228850},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaudhuriBKLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenBCWZZ023,
author = {Xin Chen and
Yuxin Bai and
Jianpeng Cao and
Lei Wang and
Xinjie Zhou and
Ying Zhang and
Weiqiang Liu},
title = {Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1039--1050},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3274632},
doi = {10.1109/TVLSI.2023.3274632},
timestamp = {Fri, 06 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenBCWZZ023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenGWLL23,
author = {Ke Chen and
Yue Gao and
Haroon Waris and
Weiqiang Liu and
Fabrizio Lombardi},
title = {Approximate Softmax Functions for Energy-Efficient Deep Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {4--16},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224011},
doi = {10.1109/TVLSI.2022.3224011},
timestamp = {Wed, 22 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenGWLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLCC23,
author = {Kexu Chen and
Di Li and
Dongdong Chen and
Changchun Chai},
title = {An Improved {MOS} Self-Biased Ring Amplifier and Modified Auto-Zeroing
Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {606--610},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3242821},
doi = {10.1109/TVLSI.2023.3242821},
timestamp = {Fri, 26 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLCW23,
author = {Kun{-}Chih Chen and
Yuan{-}Hao Liao and
Cheng{-}Ting Chen and
Leiqi Wang},
title = {Adaptive Machine Learning-Based Proactive Thermal Management for NoC
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1114--1127},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3282969},
doi = {10.1109/TVLSI.2023.3282969},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLCW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLFTBR23,
author = {Jie Chen and
Igor Loi and
Eric Flamand and
Giuseppe Tagliavini and
Luca Benini and
Davide Rossi},
title = {Scalable Hierarchical Instruction Cache for Ultralow-Power Processors
Clusters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {456--469},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3228336},
doi = {10.1109/TVLSI.2022.3228336},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLFTBR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenSWL23,
author = {Yangyang Chen and
Suwen Song and
Zhongfeng Wang and
Jun Lin},
title = {An Efficient Massive {MIMO} Detector Based on Approximate Expectation
Propagation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {696--700},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3255234},
doi = {10.1109/TVLSI.2023.3255234},
timestamp = {Thu, 10 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenSWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWZLTD23,
author = {Zhuojun Chen and
Ming Wu and
Yifeng Zhou and
Renlong Li and
Jinzhe Tan and
Ding Ding},
title = {{PUF-CIM:} SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical
Unclonable Function for Lightweight Secure Edge Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1234--1247},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3277517},
doi = {10.1109/TVLSI.2023.3277517},
timestamp = {Mon, 30 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWZLTD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChouCC23,
author = {Yu{-}Jie Chou and
Hsiao{-}Chin Chen and
Yan{-}Ming Chang},
title = {Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1330--1338},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3290262},
doi = {10.1109/TVLSI.2023.3290262},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChouCC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChuKLL23,
author = {Shao{-}I Chu and
Syuan{-}An Ke and
Sheng{-}Jung Liu and
Yan{-}Wei Lin},
title = {An Efficient Hard-Detection {GRAND} Decoder for Systematic Linear
Block Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1852--1864},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3300568},
doi = {10.1109/TVLSI.2023.3300568},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChuKLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChunRCCMMM23,
author = {Alexander Choo Chia Chun and
Harikrishnan Ramiah and
Kishore Kumar Pakkirisami Churchill and
Yong Chen and
Saad Mekhilef and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A High-Performance Dual-Topology {CMOS} Rectifier With 19.5-dB Power
Dynamic Range for RF-Based Hybrid Energy Harvesting},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1253--1257},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3261263},
doi = {10.1109/TVLSI.2023.3261263},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChunRCCMMM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChurchillRCCCMM23,
author = {Kishore Kumar Pakkirisami Churchill and
Harikrishnan Ramiah and
Alexander Choo Chia Chun and
Gabriel Chong and
Yong Chen and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A Reconfigurable {CMOS} Stack Rectifier With 22.8-dB Dynamic Range
Achieving 47.91{\%} Peak {PCE} for IoT/WSN Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1619--1623},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3299075},
doi = {10.1109/TVLSI.2023.3299075},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChurchillRCCCMM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CollemanSV23,
author = {Steven Colleman and
Man Shi and
Marian Verhelst},
title = {{COAC:} Cross-Layer Optimization of Accelerator Configurability for
Efficient {CNN} Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {945--958},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3268084},
doi = {10.1109/TVLSI.2023.3268084},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CollemanSV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DalinH23,
author = {Elamana Marakkadath Dalin and
S. M. Rezaul Hasan},
title = {A Low Phase-Lag Self-Powered {SECE} Interface Circuit for Pressure-Type
Piezoelectric Energy-Harvesting Compatible With {COTS} Pressure Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1634--1638},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3280923},
doi = {10.1109/TVLSI.2023.3280923},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DalinH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DavilaWJCT23,
author = {Henry Lopez Davila and
Tsung{-}Han Wu and
Shyh{-}Jye Jou and
Sau{-}Gee Chen and
Pei{-}Yun Tsai},
title = {Low Routing Complexity Multiframe Pipelined {LDPC} Decoder Based on
a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {29--42},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224084},
doi = {10.1109/TVLSI.2022.3224084},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DavilaWJCT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DingDHCWLL23,
author = {Haofan Ding and
Haiyan Dai and
Xin Hong and
Deyan Chen and
Junyuan Wu and
Jinghu Li and
Zhicong Luo},
title = {A 10-Gb/s Inductorless Low-Power {TIA} With a 400-fF Low-Speed Avalanche
Photodiode Realized in {CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {512--521},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3237801},
doi = {10.1109/TVLSI.2023.3237801},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DingDHCWLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DominguezMatasGOGLP23,
author = {Carlos Manuel Dom{\'{\i}}nguez{-}Matas and
Antonio J. Gin{\'{e}}s and
Ar{\'{a}}nzazu Ot{\'{\i}}n and
Valentin Gutierrez and
Gildas L{\'{e}}ger and
Eduardo J. Peral{\'{\i}}as},
title = {Behavioral Model for High-Speed {SAR} ADCs With On-Chip References},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1918--1930},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3314067},
doi = {10.1109/TVLSI.2023.3314067},
timestamp = {Sun, 17 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DominguezMatasGOGLP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongreBT23,
author = {Ashvinikumar Dongre and
Bipul Boro and
Gaurav Trivedi},
title = {ADC-Less Reprogrammable {RRAM} Array Architecture for In-Memory Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2053--2060},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3319578},
doi = {10.1109/TVLSI.2023.3319578},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DongreBT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EggersglussMRT23,
author = {Stephan Eggersgl{\"{u}}{\ss} and
Sylwester Milewski and
Janusz Rajski and
Jerzy Tyszer},
title = {A New Static Compaction of Deterministic Test Sets},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {411--420},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3240246},
doi = {10.1109/TVLSI.2023.3240246},
timestamp = {Sat, 29 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EggersglussMRT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FarheenRTF23,
author = {Tasnuva Farheen and
Sourav Roy and
Shahin Tajik and
Domenic Forte},
title = {A Twofold Clock and Voltage-Based Detection Method for Laser Logic
State Imaging Attack},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {65--78},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3214724},
doi = {10.1109/TVLSI.2022.3214724},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FarheenRTF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FilippasND23,
author = {Dionysios Filippas and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Streaming Dilated Convolution Engine},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {401--405},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3233882},
doi = {10.1109/TVLSI.2022.3233882},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FilippasND23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ForntFCAMAS23,
author = {Jordi Fornt and
Pau Fontova{-}Must{\'{e}} and
Mart{\'{\i}} Caro and
Jaume Abella and
Francesc Moll and
Josep Altet and
Christoph Studer},
title = {An Energy-Efficient GeMM-Based Convolution Accelerator With On-the-Fly
im2col},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1874--1878},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3286122},
doi = {10.1109/TVLSI.2023.3286122},
timestamp = {Sat, 28 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ForntFCAMAS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuHSMLY23,
author = {Yushen Fu and
Chengyu Huang and
Limeng Sun and
Weiguang Meng and
Xueqing Li and
Huazhong Yang},
title = {A 6.0-GS/s Time-Interleaved {DAC} Using an Asymmetric Current-Tree
Summation Network and Differential Clock Timing Calibration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {199--209},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3232516},
doi = {10.1109/TVLSI.2022.3232516},
timestamp = {Thu, 19 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FuHSMLY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuLZLMZZW23,
author = {Siqing Fu and
Tiejun Li and
Chunyuan Zhang and
Hanqing Li and
Sheng Ma and
Jianmin Zhang and
Ruiyi Zhang and
Lizhou Wu},
title = {{RHS-TRNG:} {A} Resilient High-Speed True Random Number Generator
Based on {STT-MTJ} Device},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1578--1591},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3298327},
doi = {10.1109/TVLSI.2023.3298327},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FuLZLMZZW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaoSLUR23,
author = {Zhen Gao and
Jinchang Shi and
Qiang Liu and
Anees Ullah and
Pedro Reviriego},
title = {Reliability Evaluation and Fault Tolerance Design for {FPGA} Implemented
Reed Solomon {(RS)} Erasure Decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {142--146},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224137},
doi = {10.1109/TVLSI.2022.3224137},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GaoSLUR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GeSTE23,
author = {Yang Ge and
Tejinder Singh Sandhu and
Dmitri V. Truhachev and
Kamal El{-}Sankary},
title = {A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies
Clock Synchronization in 3-D-ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {567--577},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244489},
doi = {10.1109/TVLSI.2023.3244489},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GeSTE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GengCZDD23,
author = {Haoran Geng and
Xiaoliang Chen and
Ning Zhao and
Yuan Du and
Li Du},
title = {{QPA:} {A} Quantization-Aware Piecewise Polynomial Approximation Methodology
for Hardware-Efficient Implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {931--944},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3277023},
doi = {10.1109/TVLSI.2023.3277023},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GengCZDD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GoebelAZP23,
author = {Jones William Goebel and
Luciano Volcan Agostini and
Bruno Zatt and
Marcelo Schiavon Porto},
title = {A High-Throughput Hardware Design for the {AV1} Decoder Intraprediction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {498--511},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3239388},
doi = {10.1109/TVLSI.2023.3239388},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GoebelAZP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GongLWCW23,
author = {Jiuxin Gong and
Zhaoming Lu and
Luhan Wang and
Xinghe Chu and
Xiangming Wen},
title = {A Reusable and Efficient Architecture for {QC-LDPC} Encoder With Less
Expansion Factors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2089--2101},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3318852},
doi = {10.1109/TVLSI.2023.3318852},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GongLWCW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GoreTG23,
author = {Ganesh Gore and
Xifan Tang and
Pierre{-}Emmanuel Gaillardon},
title = {A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom
{FPGA} Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1128--1139},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3270448},
doi = {10.1109/TVLSI.2023.3270448},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GoreTG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuanTLZZ23,
author = {Wenbo Guan and
Xiaoyan Tang and
Hongliang Lu and
Yuming Zhang and
Yimen Zhang},
title = {A Novel Thermal-Aware Floorplanning and {TSV} Assignment With Game
Theory for Fixed-Outline 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1639--1652},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3309595},
doi = {10.1109/TVLSI.2023.3309595},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuanTLZZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuanTLZZ23a,
author = {Wenbo Guan and
Xiaoyan Tang and
Hongliang Lu and
Yuming Zhang and
Yimen Zhang},
title = {Thermal-Aware Fixed-Outline 3-D {IC} Floorplanning: An End-to-End
Learning-Based Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1882--1895},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3321532},
doi = {10.1109/TVLSI.2023.3321532},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuanTLZZ23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuanTLZZ23b,
author = {Wenbo Guan and
Xiaoyan Tang and
Hongliang Lu and
Yuming Zhang and
Yimen Zhang},
title = {{ATT-TA:} {A} Cooperative Multiagent Deep Reinforcement Learning Approach
for {TSV} Assignment in 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1905--1917},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3321536},
doi = {10.1109/TVLSI.2023.3321536},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuanTLZZ23b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoWHLQL23,
author = {Yifan Guo and
Zhijun Wang and
Qinzhi Hong and
Hanqing Luo and
Xin Qiu and
Liping Liang},
title = {A 60-Mode High-Throughput Parallel-Processing {FFT} Processor for
5G/4G Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {219--232},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3227346},
doi = {10.1109/TVLSI.2022.3227346},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoWHLQL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanCLC23,
author = {Sangwoo Han and
Minjung Cho and
Gi Lee and
Eui{-}Young Chung},
title = {Page Type-Aware Data Migration Technique for Read Disturb Management
of {NAND} Flash Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {591--595},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3240172},
doi = {10.1109/TVLSI.2023.3240172},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HanCLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanJ23,
author = {Shaopu Han and
Yanfeng Jiang},
title = {RISC-V-Based Evaluation and Strategy Exploration of {MRAM} Triple-Level
Hybrid Cache Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {980--992},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3268108},
doi = {10.1109/TVLSI.2023.3268108},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HanJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaoSXZZF23,
author = {Zhijian Hao and
Heming Sun and
Guoqing Xiang and
Peng Zhang and
Xiaoyang Zeng and
Yibo Fan},
title = {A Reconfigurable Multiple Transform Selection Architecture for {VVC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {658--669},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3245291},
doi = {10.1109/TVLSI.2023.3245291},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HaoSXZZF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HaqGSDSC23,
author = {Syed Asrar ul Haq and
Abdul Karim Gizzini and
Shakti Shrey and
Sumit Jagdish Darak and
Sneh Saurabh and
Marwa Chafii},
title = {Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based
{OFDM} {PHY} on Zynq System on Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1026--1038},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3274555},
doi = {10.1109/TVLSI.2023.3274555},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HaqGSDSC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeTBSX23,
author = {Pengzhou He and
Yazheng Tu and
Tianyou Bao and
Leonel Sousa and
Jiafeng Xie},
title = {{COPMA:} Compact and Optimized Polynomial Multiplier Accelerator for
High-Performance Implementation of LWR-Based {PQC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {596--600},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3242640},
doi = {10.1109/TVLSI.2023.3242640},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeTBSX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeTXJ23,
author = {Pengzhou He and
Yazheng Tu and
Jiafeng Xie and
H. S. Jacinto},
title = {{KINA:} Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE
(RBLWE)-Based Post-Quantum Cryptography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1551--1564},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3302289},
doi = {10.1109/TVLSI.2023.3302289},
timestamp = {Wed, 01 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeTXJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HsuLCH23,
author = {Pai{-}Hsiang Hsu and
Yueh{-}Ru Lee and
Chia{-}Hung Chen and
Chung{-}Chih Hung},
title = {A Low-Noise Area-Efficient Column-Parallel {ADC} With an Input Triplet
for a 120-dB High Dynamic Range {CMOS} Image Sensor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1939--1949},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3323363},
doi = {10.1109/TVLSI.2023.3323363},
timestamp = {Wed, 13 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HsuLCH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuWWZDYPXD23,
author = {Hongyang Hu and
Xiwei Wang and
Zi Wang and
Haiyang Zhou and
Danian Dong and
Jinshan Yue and
Wan Pang and
Xiaoxin Xu and
Chunmeng Dou},
title = {A 40-nm {SONOS} Digital {CIM} Using Simplified {LUT} Multiplier and
Continuous Sample-Hold Sense Amplifier for {AI} Edge Inference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2044--2052},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3305530},
doi = {10.1109/TVLSI.2023.3305530},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuWWZDYPXD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangCZMM23,
author = {Yunbo Huang and
Yong Chen and
Bo Zhao and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A 3.6-GHz Type-II Sampling {PLL} With a Differential Parallel-Series
Double-Edge {S-PD} Scoring 43.1-fs\({}_{\mbox{RMS}}\)Jitter, -258.7-dB
FOM, and -75.17-dBc Reference Spur},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {188--198},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3229342},
doi = {10.1109/TVLSI.2022.3229342},
timestamp = {Thu, 02 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangCZMM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangHC23,
author = {An{-}Jung Huang and
Jo{-}Hsuan Hung and
Tian{-}Sheuan Chang},
title = {Memory Bandwidth Efficient Design for Super-Resolution Accelerators
With Structure Adaptive Fusion and Channel-Aware Addressing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {802--811},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3253803},
doi = {10.1109/TVLSI.2023.3253803},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangHC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangJDDWC23,
author = {Xiangrong Huang and
Haikun Jia and
Shengnan Dong and
Wei Deng and
Zhihua Wang and
Baoyong Chi},
title = {A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion
Loss Compact {T/R} Switch and Bidirectional Phase Shifter for 5G Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1839--1851},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3308720},
doi = {10.1109/TVLSI.2023.3308720},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangJDDWC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HungCLYTC23,
author = {Wei{-}Tse Hung and
Yu{-}Guang Chen and
Jhen{-}Gang Lin and
Yun{-}Wei Yang and
Cheng{-}Hong Tsai and
Mango Chia{-}Tso Chao},
title = {{DRC} Violation Prediction After Global Route Through Convolutional
Neural Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1425--1438},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3271932},
doi = {10.1109/TVLSI.2023.3271932},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HungCLYTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuntSchroederX23,
author = {Eric Hunt{-}Schroeder and
Tian Xia},
title = {12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct
Capability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {840--850},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244860},
doi = {10.1109/TVLSI.2023.3244860},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuntSchroederX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangWJP23,
author = {Young{-}Ha Hwang and
Jun Wang and
Deog{-}Kyoon Jeong and
Jun{-}Eun Park},
title = {An Area/Power-Efficient {\(\Delta\)}{\(\Sigma\)} Modulator Based on
Dynamic-Boost Inverter for Multichannel Sensor Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1403--1412},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3294914},
doi = {10.1109/TVLSI.2023.3294914},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangWJP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IshdorjN23,
author = {Bayartulga Ishdorj and
Taehui Na},
title = {Spin-Transfer-Torque Magnetic-Tunnel-Junction-Based Low-Power Nonvolatile
Flip-Flop Designs in the Subthreshold Voltage Region},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1565--1577},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3300032},
doi = {10.1109/TVLSI.2023.3300032},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/IshdorjN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainTCMBFWSANHI23,
author = {Shubham Jain and
Hsinyu Tsai and
Ching{-}Tzu Chen and
Ramachandran Muralidhar and
Irem Boybat and
Martin M. Frank and
Stanislaw Wozniak and
Milos Stanisavljevic and
Praneet Adusumilli and
Pritish Narayanan and
Kohji Hosokawa and
Masatoshi Ishii and
Arvind Kumar and
Vijay Narayanan and
Geoffrey W. Burr},
title = {A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture
for Analog-AI Using Dense 2-D Mesh},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {114--127},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3221390},
doi = {10.1109/TVLSI.2022.3221390},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JainTCMBFWSANHI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JanvejaSBPT23,
author = {Meenali Janveja and
Ashwani Kumar Sharma and
Abhyuday Bhardwaj and
Jan Pidanic and
Gaurav Trivedi},
title = {An Optimized Low-Power {VLSI} Architecture for {ECG/VCG} Data Compression
for IoHT Wearable Device Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2008--2015},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3314611},
doi = {10.1109/TVLSI.2023.3314611},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JanvejaSBPT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JayasenaAM23,
author = {Aruna Jayasena and
Emma Andrews and
Prabhat Mishra},
title = {TVLA*: Test Vector Leakage Assessment on Hardware Implementations
of Asymmetric Cryptography Algorithms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1269--1279},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3297027},
doi = {10.1109/TVLSI.2023.3297027},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JayasenaAM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JeongKP23,
author = {Eunsol Jeong and
Taewhan Kim and
Heechun Park},
title = {Eliminating Minimum Implant Area Violations With Design Quality Preservation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {611--621},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3225551},
doi = {10.1109/TVLSI.2022.3225551},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JeongKP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JingZYL23,
author = {Peng Jing and
Wei Zhang and
Long Yan and
Yanyan Liu},
title = {{VLSI} Design of a High-Performance Multicontext {MQ} Arithmetic Coder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {396--400},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3234023},
doi = {10.1109/TVLSI.2023.3234023},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JingZYL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KaliSM23,
author = {Anil Kali and
Samrat L. Sabat and
Pramod Kumar Meher},
title = {Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product
of Variable Vectors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1368--1376},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3294571},
doi = {10.1109/TVLSI.2023.3294571},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KaliSM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KameiAKYUHSB23,
author = {Aika Kamei and
Hideharu Amano and
Takuya Kojima and
Daiki Yokoyama and
Kimiyoshi Usami and
Keizo Hiraga and
Kenta Suzuki and
Kazuhiro Bessho},
title = {A Variation-Aware {MTJ} Store Energy Estimation Model for Edge Devices
With Verify-and-Retryable Nonvolatile Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {532--542},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3237794},
doi = {10.1109/TVLSI.2023.3237794},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KameiAKYUHSB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KashikarSS23,
author = {Prachi Kashikar and
Olivier Sentieys and
Sharad Sinha},
title = {Lossless Neural Network Model Compression Through Exponent Sharing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1816--1825},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3307607},
doi = {10.1109/TVLSI.2023.3307607},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KashikarSS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KeranD23,
author = {Mark Keran and
Anestis Dounavis},
title = {An Analytic {RLC} Model for Coupled Interconnects Which Uses a Numerical
Inverse Laplace Transform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1497--1508},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3288732},
doi = {10.1109/TVLSI.2023.3288732},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KeranD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhalifaHLHPYK23,
author = {Marcel Khalifa and
Barak Hoffer and
Orian Leitersdorf and
Robert Hanhan and
Ben Perach and
Leonid Yavits and
Shahar Kvatinsky},
title = {ClaPIM: Scalable Sequence Classification Using Processing-in-Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1347--1357},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3293038},
doi = {10.1109/TVLSI.2023.3293038},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhalifaHLHPYK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KilianTHHS23,
author = {Tobias Kilian and
Daniel Tille and
Martin Huch and
Markus Hanel and
Ulf Schlichtmann},
title = {Performance Screening Using Functional Path Ring Oscillators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {711--724},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3252471},
doi = {10.1109/TVLSI.2023.3252471},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KilianTHHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimHKL23,
author = {Woojung Kim and
Woojin Hong and
Jae Joon Kim and
Myunghee Lee},
title = {A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless {CDR} With an Unlimited
Bilateral Frequency Detection Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {851--860},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3266352},
doi = {10.1109/TVLSI.2023.3266352},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimHKL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimJWYKNLSKROS23,
author = {Taehak Kim and
Jaehoon Jeong and
Seungmin Woo and
Jeonggyu Yang and
Hyunwoo Kim and
Ahyeon Nam and
Changdong Lee and
Jinmin Seo and
Minji Kim and
Siwon Ryu and
Yoonju Oh and
Taigon Song},
title = {{NS3K:} {A} 3-nm Nanosheet {FET} Standard Cell Library Development
and its Impact},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {163--176},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3229442},
doi = {10.1109/TVLSI.2022.3229442},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimJWYKNLSKROS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSLK23,
author = {Kwangmin Kim and
Hyoseok Song and
Byeongcheol Lee and
Byungsub Kim},
title = {A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal
Circuits: {A} High-Speed {FFE} {SST} Transmitter Example},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {622--635},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3251946},
doi = {10.1109/TVLSI.2023.3251946},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSLK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KocamanG23,
author = {Namik K. Kocaman and
Michael M. Green},
title = {Asynchronous Sampling-Based Hybrid Equalizer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1014--1025},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3273182},
doi = {10.1109/TVLSI.2023.3273182},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KocamanG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KooS23,
author = {Jahyun Koo and
Jae{-}Yoon Sim},
title = {Corrections to "Low-Noise Distributed {RC} Oscillator"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {286},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3229577},
doi = {10.1109/TVLSI.2022.3229577},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KooS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KrishnaN23,
author = {Komala Krishna and
Nandakumar Nambath},
title = {Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm
{CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1083--1086},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3276000},
doi = {10.1109/TVLSI.2023.3276000},
timestamp = {Wed, 12 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KrishnaN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeHK23,
author = {Youngkwang Lee and
Donghyun Han and
Sungho Kang},
title = {{TSV} Built-In Self-Repair Architecture for Improving the Yield and
Reliability of {HBM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {578--590},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3248042},
doi = {10.1109/TVLSI.2023.3248042},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeHK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeJKP23,
author = {Hee Sung Lee and
Tae Hwan Jang and
Joon Hyung Kim and
Chul Soon Park},
title = {Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned {VCO}
Assisting With g\({}_{\mbox{m}}\)-Boosting Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1629--1633},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3294404},
doi = {10.1109/TVLSI.2023.3294404},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeJKP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeK23,
author = {Cheng{-}Yen Lee and
Sunil P. Khatri},
title = {A Digital Low Dropout {(LDO)} Voltage Regulator Using Pseudoflash
Transistors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1960--1969},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3317414},
doi = {10.1109/TVLSI.2023.3317414},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeKAKJ23,
author = {Wonjae Lee and
Kukbyung Kim and
Woohyun Ahn and
Jinho Kim and
Dongsuk Jeon},
title = {A Real-Time Object Detection Processor With xnor-Based Variable-Precision
Computing Unit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {749--761},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3257198},
doi = {10.1109/TVLSI.2023.3257198},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeKAKJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeighHM23,
author = {Alexander J. Leigh and
Moslem Heidarpur and
Mitra Mirhassani},
title = {A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation
of the Hodgkin-Huxley Neuron},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1377--1388},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3296057},
doi = {10.1109/TVLSI.2023.3296057},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeighHM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiKL23,
author = {Yuyang Li and
Yejoong Kim and
Inhee Lee},
title = {A 5-mm\({}^{\mbox{2}}\), 4.7-{\(\mu\)}W Convolutional Neural Network
Layer Accelerator for Miniature Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2142--2146},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3324572},
doi = {10.1109/TVLSI.2023.3324572},
timestamp = {Thu, 14 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiKL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLWDL23,
author = {Hongyan Li and
Hang Lu and
Haoxuan Wang and
Shengji Deng and
Xiaowei Li},
title = {BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural
Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {90--103},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3221732},
doi = {10.1109/TVLSI.2022.3221732},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLWDL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiMRKBY23,
author = {Wantong Li and
Madison Manley and
James Read and
Ankit Kaul and
Muhannad S. Bakir and
Shimeng Yu},
title = {H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory
Accelerator for Vision Transformer Self-Attention},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1592--1602},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3299509},
doi = {10.1109/TVLSI.2023.3299509},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiMRKBY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiMYE23,
author = {Tao Li and
Yitao Ma and
Ko Yoshikawa and
Tetsuo Endoh},
title = {Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer
Multiplier for Energy-Efficient STT-MRAM-Based {AI} Accelerator"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {906},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3264100},
doi = {10.1109/TVLSI.2023.3264100},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiMYE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiSZZZ23,
author = {Jindong Li and
Guobin Shen and
Dongcheng Zhao and
Qian Zhang and
Yi Zeng},
title = {FireFly: {A} High-Throughput Hardware Accelerator for Spiking Neural
Networks With Efficient {DSP} and Memory Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1178--1191},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3279349},
doi = {10.1109/TVLSI.2023.3279349},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiSZZZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWLZSZ23,
author = {Baoting Li and
Hang Wang and
Fujie Luo and
Xuchong Zhang and
Hongbin Sun and
Nanning Zheng},
title = {{ACBN:} Approximate Calculated Batch Normalization for Efficient {DNN}
On-Device Training Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {738--748},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3262787},
doi = {10.1109/TVLSI.2023.3262787},
timestamp = {Mon, 05 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWLZSZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCSWZLP23,
author = {Zhiting Lin and
Min Chen and
Peng Sun and
Xiulong Wu and
Qiang Zhao and
Wenjuan Lu and
Chunyu Peng},
title = {High Restore Yield {NVSRAM} Structures With Dual Complementary {RRAM}
Devices for High-Speed Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {522--531},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3242300},
doi = {10.1109/TVLSI.2023.3242300},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCSWZLP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinTT23,
author = {Jai{-}Ming Lin and
Tsung{-}Lin Tsai and
Tsung{-}Chun Tsai},
title = {Multilevel Fixed-Outline Component Placement and Graph-Based Ball
Assignment for System in Package},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1308--1319},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3291381},
doi = {10.1109/TVLSI.2023.3291381},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinTT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinZJXLYZXFLTWLPZ23,
author = {Zhiting Lin and
Shaoying Zhang and
Qian Jin and
Jianping Xia and
Yunwei Liu and
Kefeng Yu and
Jian Zheng and
Xiaoming Xu and
Xing Fan and
Ke Li and
Zhongzhen Tong and
Xiulong Wu and
Wenjuan Lu and
Chunyu Peng and
Qiang Zhao},
title = {A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving
Multiplication Operations and Results Store},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {776--788},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3266651},
doi = {10.1109/TVLSI.2023.3266651},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinZJXLYZXFLTWLPZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LingLCQLZW23,
author = {Ming Ling and
Qingde Lin and
Ruiqi Chen and
Haimeng Qi and
Mengru Lin and
Yanxiang Zhu and
Jiansheng Wu},
title = {Vina-FPGA: {A} Hardware-Accelerated Molecular Docking Tool With Fixed-Point
Quantization and Low-Level Parallelism},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {484--497},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3217275},
doi = {10.1109/TVLSI.2022.3217275},
timestamp = {Mon, 13 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LingLCQLZW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuSXZXL23,
author = {Lianxi Liu and
Liuzhaoyu Sun and
Jiaxi Xu and
Xiatian Zhang and
Chengzhi Xu and
Xufeng Liao},
title = {A 0.4-V Startup, Dead-Zone-Free, Monolithic Four-Mode Synchronous
Buck-Boost Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1004--1013},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3271984},
doi = {10.1109/TVLSI.2023.3271984},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuSXZXL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LocatelliCE23,
author = {Pedro Sartori Locatelli and
Dalton Martini Colombo and
Kamal El{-}Sankary},
title = {Time-Domain Multiply-Accumulate Unit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {762--775},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3266743},
doi = {10.1109/TVLSI.2023.3266743},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LocatelliCE23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuZTP23,
author = {Zhifei Lu and
Wei Zhang and
He Tang and
Xizhu Peng},
title = {A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved
ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {887--891},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3235393},
doi = {10.1109/TVLSI.2023.3235393},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuZTP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuoLHRF23,
author = {Jianjun Luo and
Hailuan Liu and
Ying He and
C{\'{e}}sar Vargas Rosales and
Lingyan Fan},
title = {High-Density NVMe {SSD} With DRAM-Less eRAID Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1865--1869},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3290621},
doi = {10.1109/TVLSI.2023.3290621},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuoLHRF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MalmirG23,
author = {R. Malmir and
M. B. Ghaznavi{-}Ghoushchi},
title = {Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved
Multiple-Tail Current Mode Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1675--1685},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3305915},
doi = {10.1109/TVLSI.2023.3305915},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MalmirG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MandalNAKAO23,
author = {Sumit K. Mandal and
Shruti Yadav Narayana and
Raid Ayoub and
Michael Kishinevsky and
Ahmed Abousamra and
{\"{U}}mit Y. Ogras},
title = {Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration
and Finite Buffers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {670--683},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3250662},
doi = {10.1109/TVLSI.2023.3250662},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MandalNAKAO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MengYXWMG23,
author = {Yishuo Meng and
Chen Yang and
Siwei Xiang and
Jianfei Wang and
Kuizhi Mei and
Li Geng},
title = {An Efficient {CNN} Accelerator Achieving High {PE} Utilization Using
a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling
Workflow},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1537--1550},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3298509},
doi = {10.1109/TVLSI.2023.3298509},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MengYXWMG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuraliIZTMSKKL23,
author = {Gauthaman Murali and
Aditya Iyer and
Lingjun Zhu and
Jianming Tong and
Francisco Mu{\~{n}}oz{-}Mart{\'{\i}}nez and
Srivatsa Rangachar Srinivasa and
Tanay Karnik and
Tushar Krishna and
Sung Kyu Lim},
title = {On Continuing {DNN} Accelerator Architecture Scaling Using Tightly
Coupled Compute-on-Memory 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1603--1613},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3299564},
doi = {10.1109/TVLSI.2023.3299564},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MuraliIZTMSKKL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NguyenAAD23,
author = {Ngo{-}Doanh Nguyen and
Akram Ben Ahmed and
Abderazek Ben Abdallah and
Khanh N. Dang},
title = {Power-Aware Neuromorphic Architecture With Partial Voltage Scaling
3-D Stacking Synaptic Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2016--2029},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3318231},
doi = {10.1109/TVLSI.2023.3318231},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NguyenAAD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NietoTaladrizD23,
author = {Clara Nieto{-}Taladriz and
Wim Dehaene},
title = {Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient
Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1320--1329},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3282678},
doi = {10.1109/TVLSI.2023.3282678},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NietoTaladrizD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PapavramidouN23,
author = {Panagiota Papavramidou and
Michael Nicolaidis},
title = {Reducing Power Dissipation in Memory Repair for High Fault Rates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2112--2125},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2020.3046605},
doi = {10.1109/TVLSI.2020.3046605},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PapavramidouN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkJ23,
author = {Jihwan Park and
Hanwool Jeong},
title = {Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection
Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {701--705},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244569},
doi = {10.1109/TVLSI.2023.3244569},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkS23,
author = {Eun{-}Bin Park and
Taigon Song},
title = {Complementary {FET} {(CFET)} Standard Cell Design for Low Parasitics
and Its Impact on {VLSI} Prediction at 3-nm Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {177--187},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3220339},
doi = {10.1109/TVLSI.2022.3220339},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParmarJPT23,
author = {Rushik Parmar and
Meenali Janveja and
Jan Pidanic and
Gaurav Trivedi},
title = {Design of DNN-Based Low-Power {VLSI} Architecture to Classify Atrial
Fibrillation for Wearable Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {320--330},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3236530},
doi = {10.1109/TVLSI.2023.3236530},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParmarJPT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23,
author = {Irith Pomeranz},
title = {Path Unselection for Path Delay Fault Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {267--275},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224361},
doi = {10.1109/TVLSI.2022.3224361},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23a,
author = {Irith Pomeranz},
title = {Diagnostic Test Point Insertion and Test Compaction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {276--285},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3218924},
doi = {10.1109/TVLSI.2022.3218924},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23b,
author = {Irith Pomeranz},
title = {Sharing of Compressed Tests Among Logic Blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {421--430},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244804},
doi = {10.1109/TVLSI.2023.3244804},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23c,
author = {Irith Pomeranz},
title = {Test Data Compression for Transparent-Scan Sequences},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {601--605},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3240505},
doi = {10.1109/TVLSI.2023.3240505},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23d,
author = {Irith Pomeranz},
title = {Storage-Based Logic Built-In Self-Test With Partitioned Deterministic
Compressed Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1259--1268},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3285691},
doi = {10.1109/TVLSI.2023.3285691},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23d.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz23e,
author = {Irith Pomeranz},
title = {Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1754--1762},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3304380},
doi = {10.1109/TVLSI.2023.3304380},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz23e.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PuLLWCLX23,
author = {Yunyou Pu and
Wei Li and
Mengqi Li and
Chuangguo Wang and
Fan Chen and
Qiaoan Li and
Hongtao Xu},
title = {A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB
{HR3} and 60-dB {IMRR} in 28-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1140--1152},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3278859},
doi = {10.1109/TVLSI.2023.3278859},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PuLLWCLX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QiuMYDY23,
author = {Lei Qiu and
Tianyi Meng and
Bingbing Yao and
Zihao Du and
Xiaohua Yuan},
title = {A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common
Mode-Self-Regulation for Low-Supply-Voltage {SAR} ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {152--156},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224237},
doi = {10.1109/TVLSI.2022.3224237},
timestamp = {Sat, 19 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QiuMYDY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RRT23,
author = {Ananda Y. R. and
Nehal Raj and
Gaurav Trivedi},
title = {A {MOS-DTMOS} Implementation of Floating Memristor Emulator for High-Frequency
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {355--368},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3227201},
doi = {10.1109/TVLSI.2022.3227201},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RRT23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RajeshDJCS23,
author = {Rohith Rajesh and
Sumit Jagdish Darak and
Akshay Jain and
Shivam Chandhok and
Animesh Sharma},
title = {Hardware-Software Co-Design of Statistical and Deep-Learning Frameworks
for Wideband Sensing on Zynq System on Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {79--89},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3224582},
doi = {10.1109/TVLSI.2022.3224582},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RajeshDJCS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaoJS23,
author = {Vaibhav Venugopal Rao and
Kyle Juretus and
Ioannis Savidis},
title = {Hidden Costs of Analog Deobfuscation Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1802--1815},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3296279},
doi = {10.1109/TVLSI.2023.3296279},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RaoJS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RavipatiSSAP23,
author = {Divya Praneetha Ravipati and
Victor M. van Santen and
Sami Salamin and
Hussam Amrouch and
Preeti Ranjan Panda},
title = {Performance and Energy Studies on NC-FinFET Cache-Based Systems With
FN-McPAT},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1280--1293},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3285105},
doi = {10.1109/TVLSI.2023.3285105},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RavipatiSSAP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RenHCGWYWFXLGCZLWZCM23,
author = {Qirui Ren and
Qiang Huo and
Zhisheng Chen and
Qi Gao and
Yiming Wang and
Yiming Yang and
Hao Wu and
Xiangqu Fu and
Xiaoxin Xu and
Qing Luo and
Jianfeng Gao and
Chengying Chen and
Xiaojin Zhao and
Dengyun Lei and
Xinghua Wang and
Feng Zhang and
Yong Chen and
Pui{-}In Mak},
title = {A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant
{RFID} Tag With 16.2-{\(\mu\)}W Embedded {RRAM} and Reconfigurable
Strong {PUF}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {243--252},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3222522},
doi = {10.1109/TVLSI.2022.3222522},
timestamp = {Fri, 12 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RenHCGWYWFXLGCZLWZCM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RenaKP23,
author = {Rakesh Varma Rena and
Raviteja Kammari and
Vijay Shankar Pasupureddi},
title = {0.4-1 GHz Subsampling Mixer-First {RF} Front-End With 50-dB HRR, +10-dBm
{IB-IIP3} in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1065--1077},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3269011},
doi = {10.1109/TVLSI.2023.3269011},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RenaKP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RosaPCCSB23,
author = {Morgana Macedo Azevedo da Rosa and
Guilherme Paim and
Patr{\'{\i}}cia {\"{U}}cker Leleu da Costa and
Eduardo Antonio Cesar da Costa and
Rafael Iankowski Soares and
Sergio Bampi},
title = {AxPPA: Approximate Parallel Prefix Adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {17--28},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3218021},
doi = {10.1109/TVLSI.2022.3218021},
timestamp = {Tue, 31 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RosaPCCSB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RyuOK23,
author = {Sungju Ryu and
Youngtaek Oh and
Jae{-}Joon Kim},
title = {Binaryware: {A} High-Performance Digital Hardware Accelerator for
Binary Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2137--2141},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3324834},
doi = {10.1109/TVLSI.2023.3324834},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RyuOK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaVMRBP23,
author = {Bruno S{\'{a}} and
Luca Valente and
Jos{\'{e}} Martins and
Davide Rossi and
Luca Benini and
Sandro Pinto},
title = {{CVA6} {RISC-V} Virtualization: Architecture, Microarchitecture, and
Design Space Exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1713--1726},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3302837},
doi = {10.1109/TVLSI.2023.3302837},
timestamp = {Sat, 28 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SaVMRBP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SafariV23,
author = {Yousef Safari and
Boris Vaisband},
title = {A Robust Integrated Power Delivery Methodology for 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {287--295},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3214793},
doi = {10.1109/TVLSI.2022.3214793},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SafariV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SafiallahDPH23,
author = {Mahyar Safiallah and
Ahmad Reza Danesh and
Haoran Pu and
Payam Heydari},
title = {A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise
Cancellation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1950--1959},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3311794},
doi = {10.1109/TVLSI.2023.3311794},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SafiallahDPH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Salem23,
author = {Loai G. Salem},
title = {Analysis and Optimization of Switched-Capacitor Piezoelectric Energy
Harvesting Interface Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1389--1402},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3284429},
doi = {10.1109/TVLSI.2023.3284429},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Salem23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SamantarayER23,
author = {Aswini K. Samantaray and
Pranose J. Edavoor and
Amol D. Rahulkar},
title = {Power-Efficient {VLSI} Architecture of a New Class of Dyadic Gabor
Wavelets for Medical Image Retrieval},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {104--113},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3213186},
doi = {10.1109/TVLSI.2022.3213186},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SamantarayER23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SambangiPMMC23,
author = {Ramesh Sambangi and
Arun Sammit Pandey and
Kanchan Manna and
Sudipta Mahapatra and
Santanu Chattopadhyay},
title = {Application Mapping Onto Manycore Processor Architectures Using Active
Search Framework},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {789--801},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3239850},
doi = {10.1109/TVLSI.2023.3239850},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SambangiPMMC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeifooriOA23,
author = {Zeinab Seifoori and
Behzad Omidi and
Hossein Asadi},
title = {{PERA:} Power-Efficient Routing Architecture for SRAM-Based FPGAs
in Dark Silicon Era},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2075--2088},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3303352},
doi = {10.1109/TVLSI.2023.3303352},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeifooriOA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SenguptaCA23,
author = {Anirban Sengupta and
Rahul Chaurasia and
Aditya Anshul},
title = {Robust Security of Hardware Accelerators Using Protein Molecular Biometric
Signature and Facial Biometric Encryption Key},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {826--839},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3265559},
doi = {10.1109/TVLSI.2023.3265559},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SenguptaCA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShamsKNN23,
author = {Nakisa Shams and
Amin Pourvali Kakhki and
Morteza Nabavi and
Frederic Nabki},
title = {An {OOK} and Binary {FSK} Reconfigurable Dual-Band Noncoherent {IR-UWB}
Receiver Supporting Ternary Signaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {644--657},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3248486},
doi = {10.1109/TVLSI.2023.3248486},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShamsKNN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShamsN23,
author = {Nakisa Shams and
Frederic Nabki},
title = {Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver
Front-End for 5G Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {369--381},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3223123},
doi = {10.1109/TVLSI.2022.3223123},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShamsN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShaoLWW23,
author = {Haikuo Shao and
Jinming Lu and
Meiqi Wang and
Zhongfeng Wang},
title = {An Efficient Training Accelerator for Transformers With Hardware-Algorithm
Co-Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1788--1801},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3305569},
doi = {10.1109/TVLSI.2023.3305569},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShaoLWW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SheQW23,
author = {Rongrong She and
Hui Qian and
Zhongfeng Wang},
title = {A New {ACD-OMP} Accelerator With Clustered Computing Look-Ahead},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1449--1453},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3268667},
doi = {10.1109/TVLSI.2023.3268667},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SheQW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShenHLALDZ23,
author = {Yi Shen and
Junyan Hao and
Shubin Liu and
Zeshuai An and
Dengquan Li and
Ruixue Ding and
Zhangming Zhu},
title = {An 8-bit 1.5-GS/s Two-Step {SAR} {ADC} With Embedded Interstage Gain},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1870--1873},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3302842},
doi = {10.1109/TVLSI.2023.3302842},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShenHLALDZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SiddiqueH23,
author = {Ayesha Siddique and
Khaza Anuarul Hoque},
title = {Exposing Reliability Degradation and Mitigation in Approximate DNNs
Under Permanent Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {555--566},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3238907},
doi = {10.1109/TVLSI.2023.3238907},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SiddiqueH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SilvaPSM23,
author = {Felipe G. A. e Silva and
Alan Cadore Pinheiro and
Jarbas A. N. Silveira and
C{\'{e}}sar A. M. Marcon},
title = {A Triple Burst Error Correction Based on Region Selection Code},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1214--1222},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3273085},
doi = {10.1109/TVLSI.2023.3273085},
timestamp = {Sun, 06 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SilvaPSM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SouilemZCDH23,
author = {Malek Souilem and
Nawel Zgolli and
Telmo Reis Cunha and
Wael Dghais and
Belgacem Hamdi},
title = {Signal and Power Integrity {IO} Buffer Modeling Under Separate Power
and Ground Supply Voltage Variation of the Input and Output Stages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {874--886},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244144},
doi = {10.1109/TVLSI.2023.3244144},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SouilemZCDH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SridharanSRR23,
author = {Shrihari Sridharan and
Jacob R. Stevens and
Kaushik Roy and
Anand Raghunathan},
title = {X-Former: In-Memory Acceleration of Transformers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1223--1233},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3282046},
doi = {10.1109/TVLSI.2023.3282046},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SridharanSRR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Stan23,
author = {Mircea R. Stan},
title = {Editorial New Beginnings for {IEEE} {TVLSI}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1087--1113},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3290658},
doi = {10.1109/TVLSI.2023.3290658},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Stan23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Stan23a,
author = {Mircea R. Stan},
title = {Editorial Rolling Out the {IEEE} {TVLSI} {EDICS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1879--1881},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3324533},
doi = {10.1109/TVLSI.2023.3324533},
timestamp = {Thu, 07 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Stan23a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StangherlinWPS23,
author = {Kleber Stangherlin and
Zhuanhao Wu and
Hiren D. Patel and
Manoj Sachdev},
title = {Enhancing Strong {PUF} Security With Nonmonotonic Response Quantization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {1},
pages = {55--64},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3212271},
doi = {10.1109/TVLSI.2022.3212271},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/StangherlinWPS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StefanidisZFDS23,
author = {Apostolos Stefanidis and
Ioanna Zoumpoulidou and
Dionysios Filippas and
Giorgos Dimitrakopoulos and
Georgios Ch. Sirakoulis},
title = {Synthesis of Approximate Parallel-Prefix Adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1686--1699},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3287631},
doi = {10.1109/TVLSI.2023.3287631},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/StefanidisZFDS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SuH23,
author = {Yung{-}Chuan Su and
Shi{-}Yu Huang},
title = {A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using
One-Way Varactor Cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {343--354},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3232226},
doi = {10.1109/TVLSI.2022.3232226},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SuH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunLZSCK23,
author = {Wenhao Sun and
Deng Liu and
Zhiwei Zou and
Wendi Sun and
Song Chen and
Yi Kang},
title = {Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic
Arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {470--483},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3241933},
doi = {10.1109/TVLSI.2023.3241933},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunLZSCK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunZLKXLZD23,
author = {Lin Sun and
Zhenwei Zhang and
Lili Lang and
Tong Kang and
Wei Xiong and
Yu Liu and
Wei Zhong and
Yemin Dong},
title = {An Adaptive and Universal Timing Mismatch Estimation Method for TIADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1614--1618},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3288822},
doi = {10.1109/TVLSI.2023.3288822},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunZLKXLZD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TanTHXX23,
author = {Hongbing Tan and
Gan Tong and
Libo Huang and
Liquan Xiao and
Nong Xiao},
title = {Multiple-Mode-Supporting Floating-Point {FMA} Unit for Deep Learning
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {253--266},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3226185},
doi = {10.1109/TVLSI.2022.3226185},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TanTHXX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TanW23,
author = {Pai{-}Yu Tan and
Cheng{-}Wen Wu},
title = {A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network
Learning Core With On-Chip Spatiotemporal Back-Propagation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1994--2007},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3327417},
doi = {10.1109/TVLSI.2023.3327417},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TanW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Tang23,
author = {Song{-}Nien Tang},
title = {Area-Efficient Parallel Multiplication Units for {CNN} Accelerators
With Output Channel Parallelization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {406--410},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3235776},
doi = {10.1109/TVLSI.2023.3235776},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Tang23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThirumoorthiLHKM23,
author = {Madhan Thirumoorthi and
Alexander J. Leigh and
Moslem Heidarpur and
Mohammed A. S. Khalid and
Mitra Mirhassani},
title = {Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial
Multipliers and Their Hardware Implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1509--1522},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3299508},
doi = {10.1109/TVLSI.2023.3299508},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ThirumoorthiLHKM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TongZZLLW23,
author = {Zhongzhen Tong and
Yue Zhao and
Jin Zhang and
Zhiting Lin and
Xiaoyang Lin and
Xiulong Wu},
title = {In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry
Weight Block},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1454--1458},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3266597},
doi = {10.1109/TVLSI.2023.3266597},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TongZZLLW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TuHKX23,
author = {Yazheng Tu and
Pengzhou He and
{\c{C}}etin Kaya Ko{\c{c}} and
Jiafeng Xie},
title = {{LEAP:} Lightweight and Efficient Accelerator for Sparse Polynomial
Multiplication of {HQC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {892--896},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3246923},
doi = {10.1109/TVLSI.2023.3246923},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TuHKX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UpadhyayS23,
author = {Bharat Bhushan Upadhyay and
Kishor Sarawadekar},
title = {{VLSI} Design of Saturation-Based Image Dehazing Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {959--968},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3272018},
doi = {10.1109/TVLSI.2023.3272018},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/UpadhyayS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VaeztourshiziP23,
author = {Marzieh Vaeztourshizi and
Massoud Pedram},
title = {Efficient Error Estimation for High-Level Design Space Exploration
of Approximate Computing Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {917--930},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3273478},
doi = {10.1109/TVLSI.2023.3273478},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VaeztourshiziP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VafaeiA0H23,
author = {Jafar Vafaei and
Omid Akbari and
Muhammad Shafique and
Christian Hochberger},
title = {X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework
for Error-Tolerant Applications Deployed in Critical Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {1051--1064},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3272226},
doi = {10.1109/TVLSI.2023.3272226},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VafaeiA0H23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VenkateswarluMOVBHSBWC23,
author = {Sankatali Venkateswarlu and
Subrat Mishra and
Herman Oprins and
Bjorn Vermeersch and
Moritz Brunion and
Jun{-}Han Han and
Mircea R. Stan and
Dwaipayan Biswas and
Pieter Weckx and
Francky Catthoor},
title = {Impact of 3-D Integration on Thermal Performance of {RISC-V} MemPool
Multicore {SOC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1896--1904},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3314135},
doi = {10.1109/TVLSI.2023.3314135},
timestamp = {Sun, 17 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VenkateswarluMOVBHSBWC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VermaKDM23,
author = {Anu Verma and
Khyati Kiyawat and
Bishnu Prasad Das and
Pramod Kumar Meher},
title = {An Efficient Scaling-Free Folded Hyperbolic {CORDIC} Design Using
a Novel Low-Complexity Power-of-2 Taylor Series Approximation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1167--1177},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3281078},
doi = {10.1109/TVLSI.2023.3281078},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VermaKDM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VohraTSSD23,
author = {Sahibia Kaur Vohra and
Sherin A. Thomas and
Shivdeep and
Mahendra Sakare and
Devarshi Mrinal Das},
title = {Full {CMOS} Circuit for Brain-Inspired Associative Memory With On-Chip
Trainable Memristive {STDP} Synapse},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {7},
pages = {993--1003},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3268173},
doi = {10.1109/TVLSI.2023.3268173},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VohraTSSD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLGWC23,
author = {Jun Wang and
Yuhuan Luo and
Wenting Guo and
Feng Wu and
Xiuqin Chu},
title = {Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed
Links Based on the Minimum Required Order of the Multiple Edge Response
Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {210--218},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3225533},
doi = {10.1109/TVLSI.2022.3225533},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLGWC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangYZMS23,
author = {Jianfei Wang and
Chen Yang and
Fahong Zhang and
Yishuo Meng and
Yang Su},
title = {{TCPM:} {A} Reconfigurable and Efficient Toom-Cook-Based Polynomial
Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1153--1166},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3277865},
doi = {10.1109/TVLSI.2023.3277865},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangYZMS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZCRM23,
author = {Yujia Wang and
Jincheng Zhang and
Yong Chen and
Junyan Ren and
Shunli Ma},
title = {A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching
Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {2},
pages = {233--242},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2022.3225967},
doi = {10.1109/TVLSI.2022.3225967},
timestamp = {Fri, 10 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZCRM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZLCZH23,
author = {Yuqi Wang and
Shen Zhang and
Yifei Li and
Jian Chen and
Wenfeng Zhao and
Yajun Ha},
title = {A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V\({}_{\mbox{DD}}\)
Assist and Bitline Leakage Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {684--695},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3243027},
doi = {10.1109/TVLSI.2023.3243027},
timestamp = {Mon, 02 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZLCZH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZSZMWXW23,
author = {Zisong Wang and
Peiyi Zhao and
Tom Springer and
Congyi Zhu and
Jaccob Mau and
Andrew Wells and
Yinshui Xia and
Lingli Wang},
title = {Low-Power Redundant-Transition-Free {TSPC} Dual-Edge-Triggering Flip-Flop
Using Single-Transistor-Clocked Buffer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {5},
pages = {706--710},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3251286},
doi = {10.1109/TVLSI.2023.3251286},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZSZMWXW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiFLSPHQ23,
author = {Debao Wei and
Hua Feng and
Ming Liu and
Yu Song and
Zhelong Piao and
Cong Hu and
Liyan Qiao},
title = {Edge Word-Line Reliability Problem in 3-D {NAND} Flash Memory: Observations,
Analysis, and Solutions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {861--873},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3249183},
doi = {10.1109/TVLSI.2023.3249183},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiFLSPHQ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiYLBZLZCYML23,
author = {Yuchen Wei and
Shiheng Yang and
Yueduo Liu and
Rongxin Bao and
Zihao Zhu and
Jiahui Lin and
Zehao Zhang and
Yong Chen and
Jun Yin and
Pui{-}In Mak and
Qiang Li},
title = {A 0.0043-mm\({}^{\mbox{2}}\) 0.085-{\(\mu\)}W/MHz Relaxation Oscillator
Using Charge-Prestored Asymmetric Swings {R-RC} Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1248--1252},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244549},
doi = {10.1109/TVLSI.2023.3244549},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiYLBZLZCYML23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuZJL23,
author = {Zhuolun Wu and
Wei Zhang and
Peng Jing and
Yanyan Liu},
title = {A High-Performance Dual-Context {MQ} Encoder Architecture Based on
Extended Lookup Table},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {897--901},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3249244},
doi = {10.1109/TVLSI.2023.3249244},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WuZJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaoYLQL23,
author = {Jie Xiao and
Yujian Yang and
Haixia Long and
Rongzhen Qin and
Jungang Lou},
title = {Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1486--1496},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3297125},
doi = {10.1109/TVLSI.2023.3297125},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaoYLQL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaoZWXFSH23,
author = {Rui Xiao and
Yewei Zhang and
Bo Wang and
Yanfeng Xu and
Jicong Fan and
Haibin Shen and
Kejie Huang},
title = {A Low-Power In-Memory Multiplication and Accumulation Array With Modified
Radix-4 Input and Canonical Signed Digit Weights},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1700--1712},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3306376},
doi = {10.1109/TVLSI.2023.3306376},
timestamp = {Thu, 20 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaoZWXFSH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiongDZWZY23,
author = {Wei Xiong and
Gang Dong and
Changle Zhi and
Yang Wang and
Zhangming Zhu and
Yintang Yang},
title = {Miniaturization Strategy for Directional Couplers Based on Through-Silicon
Via Insertion and Neuro-Transfer Function Modeling Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1653--1664},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3307792},
doi = {10.1109/TVLSI.2023.3307792},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiongDZWZY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuOZHLW23,
author = {Dongyu Xu and
Yiming Ouyang and
Wu Zhou and
Zhengfeng Huang and
Huaguo Liang and
Xiaoqing Wen},
title = {RMC{\_}NoC: {A} Reliable On-Chip Network Architecture With Reconfigurable
Multifunctional Channel},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2061--2074},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3321598},
doi = {10.1109/TVLSI.2023.3321598},
timestamp = {Sun, 17 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuOZHLW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XueLLHWLZLL23,
author = {Xinghua Xue and
Cheng Liu and
Bo Liu and
Haitong Huang and
Ying Wang and
Tao Luo and
Lei Zhang and
Huawei Li and
Xiaowei Li},
title = {Exploring Winograd Convolution for Cost-Effective Neural Network Fault
Tolerance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1763--1773},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3306894},
doi = {10.1109/TVLSI.2023.3306894},
timestamp = {Thu, 18 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XueLLHWLZLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XueLWYLZLL23,
author = {Xinghua Xue and
Cheng Liu and
Ying Wang and
Bing Yang and
Tao Luo and
Lei Zhang and
Huawei Li and
Xiaowei Li},
title = {Soft Error Reliability Analysis of Vision Transformers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2126--2136},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3317138},
doi = {10.1109/TVLSI.2023.3317138},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XueLWYLZLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XueYCL23,
author = {Jianwei Xue and
Rendong Ying and
Faquan Chen and
Peilin Liu},
title = {{SFANC:} Scalable and Flexible Architecture for Neuromorphic Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1826--1838},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3282239},
doi = {10.1109/TVLSI.2023.3282239},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XueYCL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangC23,
author = {Chih{-}Chyau Yang and
Tian{-}Sheuan Chang},
title = {A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {310--319},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3235760},
doi = {10.1109/TVLSI.2023.3235760},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/tvlsi/YangWXLG23,
author = {Chen Yang and
Junfeng Wu and
Siwei Xiang and
Liyan Liang and
Li Geng},
title = {A High-Throughput and Flexible Architecture Based on a Reconfigurable
Mixed-Radix {FFT} With Twiddle Factor Compression and Conflict-Free
Access},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {10},
pages = {1472--1485},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3298943},
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timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangWXLG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/tvlsi/YuLLCSSZ23,
author = {Zhe Yu and
Yuhua Liang and
Haotian Lan and
Li Chen and
Jiajun Song and
Shida Song and
Zhangming Zhu},
title = {A Time-Domain Reconfigurable Second-Order Noise Shaping {ADC} With
Single Fan-Out Gated Delay Cells},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {6},
pages = {902--905},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3262238},
doi = {10.1109/TVLSI.2023.3262238},
timestamp = {Fri, 02 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuLLCSSZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZeghidACS23,
author = {Medien Zeghid and
Hassan Yousif Ahmed and
Abdellah Chehri and
Anissa Sghaier},
title = {Speed/Area-Efficient {ECC} Processor Implementation Over GF(2\({}^{\mbox{m}}\))
on {FPGA} via Novel Algorithm-Architecture Co-Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {8},
pages = {1192--1203},
year = {2023},
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timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZeghidACS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/tvlsi/ZhaiC23,
author = {Jianwang Zhai and
Yici Cai},
title = {Microarchitecture Design Space Exploration via Pareto-Driven Active
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journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {11},
pages = {1727--1739},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3311620},
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timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaiC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangFZG23,
author = {Nan Zhang and
Jinghan Feng and
Peixin Zhang and
Fengkui Gong},
title = {Parallel Doubly Fed Symbol Timing Recovery Algorithm and {FPGA} Implementation
for Burst Broadband Satellite Access},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2102--2111},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3311472},
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timestamp = {Fri, 20 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangFZG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangHGWL23,
author = {Heng Zhang and
Ben He and
Xuan Guo and
Danyu Wu and
Xinyu Liu},
title = {A 1-GS/s 12-bit Single-Channel Pipelined {ADC} in 28-nm {CMOS} With
Input-Split Fully Differential Ring Amplifier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1931--1938},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3323568},
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timestamp = {Tue, 09 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangHGWL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangLHLWCX23,
author = {Yongqiang Zhang and
Siting Liu and
Jie Han and
Zhendong Lin and
Shaowei Wang and
Xin Cheng and
Guangjun Xie},
title = {An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using
Parallel Datapaths},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1439--1443},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3247739},
doi = {10.1109/TVLSI.2023.3247739},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangLHLWCX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWMY23,
author = {Yicong Zhang and
Mingyu Wang and
Yangzhan Mai and
Zhiyi Yu},
title = {TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache
Computing for Efficient Tensor Computations in GPGPUs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2030--2043},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3326741},
doi = {10.1109/TVLSI.2023.3326741},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWMY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoLWSLDZ23,
author = {Xin Zhao and
Dengquan Li and
Feida Wang and
Yi Shen and
Shubin Liu and
Ruixue Ding and
Zhangming Zhu},
title = {An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step {ADC} With Cross-Coupled
Linearized {VTC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {2147--2151},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3309651},
doi = {10.1109/TVLSI.2023.3309651},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoLWSLDZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoYXCZR23,
author = {Wenzhe Zhao and
Guoming Yang and
Tian Xia and
Fei Chen and
Nanning Zheng and
Pengju Ren},
title = {{HIPU:} {A} Hybrid Intelligent Processing Unit With Fine-Grained {ISA}
for Real-Time Deep Neural Network Inference Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1980--1993},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3327110},
doi = {10.1109/TVLSI.2023.3327110},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoYXCZR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhengBY23,
author = {Honghao Zheng and
Kang Jun Bai and
Yang Yi},
title = {Enabling a New Methodology of Neural Coding: Multiplexing Temporal
Encoding in Neuromorphic Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {3},
pages = {331--342},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3234514},
doi = {10.1109/TVLSI.2023.3234514},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhengBY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouOXHLW23,
author = {Wu Zhou and
Yiming Ouyang and
Dongyu Xu and
Zhengfeng Huang and
Huaguo Liang and
Xiaoqing Wen},
title = {Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth
Expansion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {4},
pages = {442--455},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3244859},
doi = {10.1109/TVLSI.2023.3244859},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouOXHLW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouWWPW23,
author = {Ranran Zhou and
Haozhe Wang and
Peng Wang and
Peter Poechmueller and
Yong Wang},
title = {A 55-nm Three-Stage Operational Transconductance Amplifier With Single
Cascode Miller Compensation for Large Capacitive Loads},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {12},
pages = {1970--1979},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3324893},
doi = {10.1109/TVLSI.2023.3324893},
timestamp = {Sun, 10 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouWWPW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuldassovBF23,
author = {Nurzhan Zhuldassov and
Rassul Bairamkulov and
Eby G. Friedman},
title = {Thermal Optimization of Hybrid Cryogenic Computing Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1339--1346},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3271898},
doi = {10.1109/TVLSI.2023.3271898},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuldassovBF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZouSCZWX23,
author = {Dongwei Zou and
Kezhu Song and
Zhuo Chen and
Chengyang Zhu and
Tong Wu and
Yuecheng Xu},
title = {FPGA-Based Configurable and Highly Flexible {PAM4} SerDes Simulation
System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {31},
number = {9},
pages = {1294--1307},
year = {2023},
url = {https://doi.org/10.1109/TVLSI.2023.3286803},
doi = {10.1109/TVLSI.2023.3286803},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZouSCZWX23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbbasC22,
author = {Abdullah Ibn Abbas and
Glenn E. R. Cowan},
title = {A Receiver Front-End for VCSEL-Based Optical Links With 49 {UI} Turn-On
Time},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {539--543},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3140182},
doi = {10.1109/TVLSI.2022.3140182},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AbbasC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AbbasTEJG22,
author = {Syed Mohsin Abbas and
Thibaud Tonnellier and
Furkan Ercan and
Marwan Jalaleddine and
Warren J. Gross},
title = {High-Throughput and Energy-Efficient {VLSI} Architecture for Ordered
Reliability Bits {GRAND}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {681--693},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3153605},
doi = {10.1109/TVLSI.2022.3153605},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AbbasTEJG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AdimulamS22,
author = {Mahesh Kumar Adimulam and
M. B. Srinivas},
title = {A 12-bit, 1.1-GS/s, Low-Power Flash {ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {277--290},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3138538},
doi = {10.1109/TVLSI.2021.3138538},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AdimulamS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AjirlouKSP22,
author = {Arash Fouman Ajirlou and
Farid Kenarangi and
Eli Shapira and
Inna Partin{-}Vaisband},
title = {NoD: {A} Neural Network-Over-Decoder for Edge Intelligence},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1438--1447},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3179324},
doi = {10.1109/TVLSI.2022.3179324},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AjirlouKSP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlexGMW22,
author = {Daney Alex and
Vinay Chakravarthi Gogineni and
Subrahmanyam Mula and
Stefan Werner},
title = {Novel {VLSI} Architecture for Fractional-Order Correntropy Adaptive
Filtering Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {893--904},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3169010},
doi = {10.1109/TVLSI.2022.3169010},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AlexGMW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliBDLRD22,
author = {Khaled Alhaj Ali and
Amer Baghdadi and
Elsa Dupraz and
Mathieu L{\'{e}}onardon and
Mostafa Rizk and
Jean{-}Philippe Diguet},
title = {MOL-Based In-Memory Computing of Binary Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {869--880},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3163233},
doi = {10.1109/TVLSI.2022.3163233},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AliBDLRD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliRSSRR22,
author = {Mustafa Fayez Ali and
Sourjya Roy and
Utkarsh Saxena and
Tanvi Sharma and
Anand Raghunathan and
Kaushik Roy},
title = {Compute-in-Memory Technologies and Architectures for Deep Learning
Workloads},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1615--1630},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3203583},
doi = {10.1109/TVLSI.2022.3203583},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliRSSRR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto22,
author = {Massimo Alioto},
title = {Editorial Opening of the 2022 {TVLSI} Editorial Year - Connecting
Trends From Society to {VLSI} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {1--4},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3140540},
doi = {10.1109/TVLSI.2022.3140540},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AntonovKV22,
author = {Andrei A. Antonov and
Maksim S. Karpovich and
Vladislav Yu. Vasilyev},
title = {Power-On Reset Circuit in 180-nm {CMOS} With Brownout Detection, Stable
Switching Points, Long Reset Pulse Duration, and Resilience to Switching
Noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1373--1380},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3196287},
doi = {10.1109/TVLSI.2022.3196287},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AntonovKV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ArikanPCRPBEO22,
author = {Kerem Arikan and
Alessandro Palumbo and
Luca Cassano and
Pedro Reviriego and
Salvatore Pontarelli and
Giuseppe Bianchi and
Oguz Ergin and
Marco Ottavi},
title = {Processor Security: Detecting Microarchitectural Attacks via Count-Min
Sketches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {938--951},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3171810},
doi = {10.1109/TVLSI.2022.3171810},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ArikanPCRPBEO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AtkinsonBT22,
author = {Jacob Atkinson and
Anthony Bailey and
Armin Tajalli},
title = {Systematic Design of Loop Circuit Topologies Using C/I\({}_{\mbox{DS}}\)
Methodology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1538--1542},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3181969},
doi = {10.1109/TVLSI.2022.3181969},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AtkinsonBT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaiJZCDDW22,
author = {Yichuan Bai and
Mingzhe Jiang and
Qingyu Zhu and
Xiaoliang Chen and
Yuan Du and
Li Du and
Zhongfeng Wang},
title = {An Efficient High-Throughput Structured-Light Depth Engine},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1047--1058},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3171854},
doi = {10.1109/TVLSI.2022.3171854},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaiJZCDDW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhattacharjeeC22,
author = {Indranil Bhattacharjee and
Gajendranath Chowdary},
title = {A 0.3 nW, 0.093{\%}/V Line Sensitivity, Temperature Compensated Bulk-Programmable
Voltage Reference for Wireless Sensor Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1281--1293},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3178735},
doi = {10.1109/TVLSI.2022.3178735},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BhattacharjeeC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangNHWWHTCCC22,
author = {Shuo{-}Wen Chang and
Yu{-}Teng Nien and
Yu{-}Pang Hu and
Kai{-}Chiang Wu and
Chi Chun Wang and
Fu{-}Sheng Huang and
Yi{-}Lun Tang and
Yung{-}Chen Chen and
Ming{-}Chien Chen and
Mango C.{-}T. Chao},
title = {Test Methodology for Defect-Based Bridge Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {975--988},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3154535},
doi = {10.1109/TVLSI.2022.3154535},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangNHWWHTCCC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangSCTYWH22,
author = {Kuo{-}Wei Chang and
Hsu{-}Tung Shih and
Tian{-}Sheuan Chang and
Shang{-}Hong Tsai and
Chih{-}Chyau Yang and
Chien{-}Ming Wu and
Chun{-}Ming Huang},
title = {A Real-Time 1280 {\texttimes} 720 Object Detection Chip With 585 MB/s
Memory Traffic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {816--825},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3149768},
doi = {10.1109/TVLSI.2022.3149768},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangSCTYWH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CharlesBM22,
author = {Subodha Charles and
Vincent Bindschaedler and
Prabhat Mishra},
title = {Digital Watermarking for Detecting Malicious Intellectual Property
Cores in NoC Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {952--965},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3167606},
doi = {10.1109/TVLSI.2022.3167606},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CharlesBM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChatterjeeR22,
author = {Shatadal Chatterjee and
Sounak Roy},
title = {A Self-Calibration Method of a Pipeline {ADC} Based on Dynamic Capacitance
Allotment},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {666--670},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151479},
doi = {10.1109/TVLSI.2022.3151479},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChatterjeeR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaurasiyaS22,
author = {Rohit B. Chaurasiya and
Rahul Shrestha},
title = {Hardware-Efficient {VLSI} Architecture and {ASIC} Implementation of
GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {166--176},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3114859},
doi = {10.1109/TVLSI.2021.3114859},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaurasiyaS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCLCELXGNDAT22,
author = {Rongmei Chen and
Lin Chen and
Jie Liang and
Yuanqing Cheng and
Souhir Elloumi and
Jaehyun Lee and
Kangwei Xu and
Vihar P. Georgiev and
Kai Ni and
Peter Debacker and
Asen Asenov and
Aida Todri{-}Sanial},
title = {Carbon Nanotube {SRAM} in 5-nm Technology Node Design, Optimization,
and Performance Evaluation - Part {I:} {CNFET} Transistor Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {432--439},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3146125},
doi = {10.1109/TVLSI.2022.3146125},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCLCELXGNDAT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCLCELXGNDAT22a,
author = {Rongmei Chen and
Lin Chen and
Jie Liang and
Yuanqing Cheng and
Souhir Elloumi and
Jaehyun Lee and
Kangwei Xu and
Vihar P. Georgiev and
Kai Ni and
Peter Debacker and
Asen Asenov and
Aida Todri{-}Sanial},
title = {Carbon Nanotube {SRAM} in 5-nm Technology Node Design, Optimization,
and Performance Evaluation - Part {II:} {CNT} Interconnect Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {440--448},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3146064},
doi = {10.1109/TVLSI.2022.3146064},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCLCELXGNDAT22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCW22,
author = {Yuxing Chen and
Hangxuan Cui and
Zhongfeng Wang},
title = {An Efficient Reconfigurable Encoder for the {IEEE} 1901 Standard},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1368--1372},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3177239},
doi = {10.1109/TVLSI.2022.3177239},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenGF22,
author = {Qinyu Chen and
Chang Gao and
Yuxiang Fu},
title = {Cerebron: {A} Reconfigurable Architecture for Spatiotemporal Sparse
Spiking Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1425--1437},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3196839},
doi = {10.1109/TVLSI.2022.3196839},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenGF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenL22,
author = {Yuhao Chen and
Hongge Li},
title = {Stochastic Computing Using Amplitude and Frequency Encoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {656--660},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3150569},
doi = {10.1109/TVLSI.2022.3150569},
timestamp = {Tue, 12 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenNJ22,
author = {Yuting Chen and
Yuxuan Nie and
Hailong Jiao},
title = {An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold
Digital Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {676--680},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151500},
doi = {10.1109/TVLSI.2022.3151500},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenNJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenPL22,
author = {Yan{-}Ting Chen and
Pen{-}Jui Peng and
Hung{-}Wen Lin},
title = {A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling {PLL} With
a High-Linearity Phase Interpolator in 40-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {634--643},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3160327},
doi = {10.1109/TVLSI.2022.3160327},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenPL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenZWSJH22,
author = {Jian Chen and
Wenfeng Zhao and
Yuqi Wang and
Yuhao Shu and
Weixiong Jiang and
Yajun Ha},
title = {A Reliable 8T {SRAM} for High-Speed Searching and Logic-in-Memory
Operations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {769--780},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3164756},
doi = {10.1109/TVLSI.2022.3164756},
timestamp = {Mon, 02 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenZWSJH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengHHLL22,
author = {Chung{-}Kuan Cheng and
Chia{-}Tung Ho and
Chester Holtz and
Daeyeal Lee and
Bill Lin},
title = {Machine Learning Prediction for Design and System Technology Co-Optimization
Sensitivity Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1059--1072},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3172938},
doi = {10.1109/TVLSI.2022.3172938},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengHHLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChiangCJ22,
author = {Yu{-}Hsiang Chiang and
Tian{-}Sheuan Chang and
Shyh{-}Jye Jou},
title = {A 14 {\(\mu\)}J/Decision Keyword-Spotting Accelerator With In-SRAMComputing
and On-Chip Learning for Customization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1184--1192},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3172685},
doi = {10.1109/TVLSI.2022.3172685},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChiangCJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChuSZXWL22,
author = {Zhufei Chu and
Chuanhe Shang and
Tingting Zhang and
Yinshui Xia and
Lunyao Wang and
Weiqiang Liu},
title = {Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1827--1839},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3210252},
doi = {10.1109/TVLSI.2022.3210252},
timestamp = {Wed, 22 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChuSZXWL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChunRCCMMM22,
author = {Alexander Choo Chia Chun and
Harikrishnan Ramiah and
Kishore Kumar Pakkirisami Churchill and
Yong Chen and
Saad Mekhilef and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A Reconfigurable {CMOS} Rectifier With 14-dB Power Dynamic Range Achieving
{\textgreater}36-dB/mm\({}^{\mbox{2}}\) FoM for RF-Based Hybrid Energy
Harvesting},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1533--1537},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3189697},
doi = {10.1109/TVLSI.2022.3189697},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChunRCCMMM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DarbaniRBL22,
author = {Paria Darbani and
Nezam Rohbani and
Hakem Beitollahi and
Pejman Lotfi{-}Kamran},
title = {{RASHT:} {A} Partially Reconfigurable Architecture for Efficient Implementation
of CNNs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {860--868},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3167449},
doi = {10.1109/TVLSI.2022.3167449},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DarbaniRBL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DhananjayPCS22,
author = {Krithika Dhananjay and
Vasilis F. Pavlidis and
Ayse K. Coskun and
Emre Salman},
title = {High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore
Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1654--1667},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3203430},
doi = {10.1109/TVLSI.2022.3203430},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DhananjayPCS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/El-Razouk22,
author = {Hayssam El{-}Razouk},
title = {Input-Latency Free Versatile Bit-Serial GF(2\({}^{\mbox{m}}\)) Polynomial
Basis Multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {589--602},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3155611},
doi = {10.1109/TVLSI.2022.3155611},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/El-Razouk22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElmitwalliNK22,
author = {Eslam Elmitwalli and
Kai Ni and
Sel{\c{c}}uk K{\"{o}}se},
title = {Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {526--538},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3144236},
doi = {10.1109/TVLSI.2022.3144236},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ElmitwalliNK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EnsanGMW22,
author = {Sina Sayyah Ensan and
Swaroop Ghosh and
Seyedhamidreza Motaman and
Derek Weast},
title = {Addressing Resiliency of In-Memory Floating Point Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1172--1183},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3170542},
doi = {10.1109/TVLSI.2022.3170542},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EnsanGMW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangWFWMLG22,
author = {Liang Fang and
Xianshan Wen and
Tao Fu and
Guanhua Wang and
Sandeep Miryala and
Tiehui Ted Liu and
Ping Gui},
title = {A 2.56-GS/s 12-bit 8x-Interleaved {ADC} With 156.6-dB FoM\({}_{\mbox{S}}\)
in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {123--133},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3133451},
doi = {10.1109/TVLSI.2021.3133451},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FangWFWMLG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FangZW22,
author = {Chao Fang and
Aojun Zhou and
Zhongfeng Wang},
title = {An Algorithm-Hardware Co-Optimized Framework for Accelerating {N:}
{M} Sparse Transformers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1573--1586},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3197282},
doi = {10.1109/TVLSI.2022.3197282},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FangZW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FengDFTBMC22,
author = {Yulang Feng and
Hao Deng and
Qingjun Fan and
Yuxuan Tang and
Phaneendra Bikkina and
Esko Mikkola and
Jinghong Chen},
title = {A 5-GS/s 6-Bit 15.07-mW Flash {ADC} With Partially Active Second-Stage
Comparison and 2{\texttimes} Time-Domain Interpolation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {625--633},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3155150},
doi = {10.1109/TVLSI.2022.3155150},
timestamp = {Thu, 16 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FengDFTBMC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FilippasMMND22,
author = {Dionysios Filippas and
Nikolaos Margomenos and
Nikolaos Mitianoudis and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {Low-Cost Online Convolution Checksum Checker},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {201--212},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3119511},
doi = {10.1109/TVLSI.2021.3119511},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FilippasMMND22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaoZYXZGWUR22,
author = {Zhen Gao and
Han Zhang and
Yi Yao and
Jiajun Xiao and
Shulin Zeng and
Guangjun Ge and
Yu Wang and
Anees Ullah and
Pedro Reviriego},
title = {Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble
Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {291--302},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3138491},
doi = {10.1109/TVLSI.2021.3138491},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaoZYXZGWUR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaodingB22,
author = {Ningcheng Gaoding and
Jean{-}Fran{\c{c}}ois Bousquet},
title = {A 4th-Order 4-Bit Continuous-Time {\(\Delta\)}{\(\Sigma\)} {ADC} Based
on Active-Passive Integrators With a Resistance Feedback {DAC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {744--754},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3155052},
doi = {10.1109/TVLSI.2022.3155052},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaodingB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhaffariCL22,
author = {Sina Ghaffari and
David W. Capson and
Kin Fun Li},
title = {A Fully Pipelined {FPGA} Architecture for Multiscale {BRISK} Descriptors
With a Novel Hardware-Aware Sampling Pattern},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {826--839},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151896},
doi = {10.1109/TVLSI.2022.3151896},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhaffariCL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GoyalPG22,
author = {Sandeep Goyal and
Ganpat Anant Parulekar and
Shalabh Gupta},
title = {A True Full-Duplex {IO} {(TFD-IO)} With Background {SI} Cancellation
for High-Density Interfaces},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {615--624},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3146326},
doi = {10.1109/TVLSI.2022.3146326},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GoyalPG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoFES22,
author = {Wenzhe Guo and
Mohammed E. Fouda and
Ahmed M. Eltawil and
Khaled Nabil Salama},
title = {Efficient Neuromorphic Hardware Through Spiking Temporal Online Local
Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1642--1653},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3208191},
doi = {10.1109/TVLSI.2022.3208191},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoFES22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HamidiD22,
author = {S. Babak Hamidi and
Debasis Dawn},
title = {A New Pathway Toward Implementing a Fully Integrated Band-Switchable
{CMOS} Power Amplifier Utilizing Bit Optimized Reconfigurable Network
{(BORN)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1294--1305},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3184245},
doi = {10.1109/TVLSI.2022.3184245},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HamidiD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HasanCCBH22,
author = {Mahmudul Hasan and
Jonathan Cruz and
Prabuddha Chakraborty and
Swarup Bhunia and
Tamzidul Hoque},
title = {Trojan Resilient Computing in {COTS} Processors Under Zero Trust},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1412--1424},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3197389},
doi = {10.1109/TVLSI.2022.3197389},
timestamp = {Wed, 01 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HasanCCBH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeidarpurM22,
author = {Moslem Heidarpur and
Mitra Mirhassani},
title = {Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based
Finite-Field Multiplier for {FPGA} Implementation"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {112},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3114580},
doi = {10.1109/TVLSI.2021.3114580},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeidarpurM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuLTW22,
author = {Xiao Hu and
Minghao Li and
Jing Tian and
Zhongfeng Wang},
title = {Efficient Homomorphic Convolution Designs on {FPGA} for Secure Inference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1691--1704},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3197895},
doi = {10.1109/TVLSI.2022.3197895},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuLTW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangCW22,
author = {Ning{-}Chi Huang and
Chao{-}Wei Cheng and
Kai{-}Chiang Wu},
title = {Timing Variability-Aware Analysis and Optimization for Variable-Latency
Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {81--94},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3109824},
doi = {10.1109/TVLSI.2021.3109824},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HwangSPJ22,
author = {Young{-}Ha Hwang and
Yoonho Song and
Jun{-}Eun Park and
Deog{-}Kyoon Jeong},
title = {A Fully Passive Noise-Shaping {SAR} {ADC} Utilizing Last-Bit Majority
Voting and Cyclic Dynamic Element Matching Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1381--1390},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3190927},
doi = {10.1109/TVLSI.2022.3190927},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HwangSPJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/InayatC22,
author = {Kashif Inayat and
Jaeyong Chung},
title = {Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {881--892},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3170233},
doi = {10.1109/TVLSI.2022.3170233},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/InayatC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IslamSC22,
author = {Md. Najrul Islam and
Rahul Shrestha and
Shubhajit Roy Chowdhury},
title = {An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient
Hardware Accelerator for Convolutional Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1891--1901},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3210963},
doi = {10.1109/TVLSI.2022.3210963},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IslamSC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JaberipurG22,
author = {Ghassem Jaberipur and
Farzad Ghazanfari},
title = {Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic
Operations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {51--59},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3120065},
doi = {10.1109/TVLSI.2021.3120065},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JaberipurG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JanaN22,
author = {Biswabandhu Jana and
Pallab Kumar Nath},
title = {A Single-Chip Solution for Diagnosing Peripheral Arterial Disease},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {671--675},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3148353},
doi = {10.1109/TVLSI.2022.3148353},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JanaN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiS22,
author = {Youngwoo Ji and
Jae{-}Yoon Sim},
title = {A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased
Compensation for Process Variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {840--843},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3158729},
doi = {10.1109/TVLSI.2022.3158729},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JiS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiangYZSLCH22,
author = {Weixiong Jiang and
Heng Yu and
Hongtu Zhang and
Yuhao Shu and
Rui Li and
Jian Chen and
Yajun Ha},
title = {{FODM:} {A} Framework for Accurate Online Delay Measurement Supporting
All Timing Paths in {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {502--514},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3144321},
doi = {10.1109/TVLSI.2022.3144321},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JiangYZSLCH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JinFLS22,
author = {Leilei Jin and
Wenjie Fu and
Ming Ling and
Longxing Shi},
title = {A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate
Activity Factors With Spark Streaming},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {353--364},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3111000},
doi = {10.1109/TVLSI.2021.3111000},
timestamp = {Tue, 01 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JinFLS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KajiyamaIYKNNNH22,
author = {Shinya Kajiyama and
Yutaka Igarashi and
Toru Yazaki and
Yusaku Katsube and
Takuma Nishimoto and
Tatsuo Nakagawa and
Yohei Nakamura and
Yoshihiro Hayashi and
Takuya Kaneko and
Hiroki Ishikuro and
Taizo Yamawaki},
title = {{T/R} Switch Composed of Three HV-MOSFETs With 12.1-{\(\mu\)}W Consumption
That Enables Per-Channel Self-Loopback {AC} Tests and -18.1-dB Switching
Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {153--165},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3129313},
doi = {10.1109/TVLSI.2021.3129313},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KajiyamaIYKNNNH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KalantariHS22,
author = {Fereshteh Kalantari and
Hossein Hosseini{-}Nejad and
Amir M. Sodagar},
title = {Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated
to Brain-Implantable Microsystems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1098--1106},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3170596},
doi = {10.1109/TVLSI.2022.3170596},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KalantariHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhalilEKB22,
author = {Kasem Khalil and
Omar Eldash and
Ashok Kumar and
Magdy A. Bayoumi},
title = {Designing Novel {AAD} Pooling in Hardware for a Convolutional Neural
Network Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {303--314},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3139904},
doi = {10.1109/TVLSI.2021.3139904},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhalilEKB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanQS22,
author = {Muhammad Rizwan Khan and
Rameesha Qaiser and
Wala Saadeh},
title = {A 380-{\(\mu\)}W Electrochemical Impedance Measurement System for
Protein Sensing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1916--1927},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3215090},
doi = {10.1109/TVLSI.2022.3215090},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanQS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhatebKAT22,
author = {Fabian Khateb and
Tomasz Kulej and
Meysam Akbari and
Kea{-}Tiong Tang},
title = {A 0.5-V Multiple-Input Bulk-Driven {OTA} in 0.18-{\(\mu\)}m {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1739--1747},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3203148},
doi = {10.1109/TVLSI.2022.3203148},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhatebKAT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KooS22,
author = {Jahyun Koo and
Jae{-}Yoon Sim},
title = {Low-Noise Distributed {RC} Oscillator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {143--152},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3131170},
doi = {10.1109/TVLSI.2021.3131170},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KooS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KroegerCGDK22,
author = {Trevor Kroeger and
Wei Cheng and
Sylvain Guilley and
Jean{-}Luc Danger and
Naghmeh Karimi},
title = {Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks
on Arbiter-PUFs and Their Derivatives},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {187--200},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3129141},
doi = {10.1109/TVLSI.2021.3129141},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KroegerCGDK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KuangCWZZLDYWH22,
author = {Yisong Kuang and
Xiaoxin Cui and
Zilin Wang and
Chenglong Zou and
Yi Zhong and
Kefei Liu and
Zhenhui Dai and
Dunshan Yu and
Yuan Wang and
Ru Huang},
title = {{ESSA:} Design of a Programmable Efficient Sparse Spiking Neural Network
Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1631--1641},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3183126},
doi = {10.1109/TVLSI.2022.3183126},
timestamp = {Tue, 04 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KuangCWZZLDYWH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KunduGLCR22,
author = {Souvik Kundu and
Priyanka B. Ganganaik and
Jeffry Louis and
Hemanth Chalamalasetty and
BVVSN Prabhakar Rao},
title = {Memristors Enabled Computing Correlation Parameter In-Memory System:
{A} Potential Alternative to Von Neumann Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {755--768},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3161847},
doi = {10.1109/TVLSI.2022.3161847},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KunduGLCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KuttappaWKT22,
author = {Ragh Kuttappa and
Longfei Wang and
Sel{\c{c}}uk K{\"{o}}se and
Baris Taskin},
title = {Multiphase Digital Low-Dropout Regulators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {40--50},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3115037},
doi = {10.1109/TVLSI.2021.3115037},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KuttappaWKT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LanzilloCBD22,
author = {Nicholas A. Lanzillo and
Albert Chu and
Prasad Bhosale and
Dan J. Dechene},
title = {Power Delivery Design, Signal Routing, and Performance of On-Chip
Cobalt Interconnects in Advanced Technology Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {60--67},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3126541},
doi = {10.1109/TVLSI.2021.3126541},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LanzilloCBD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeCLCK22,
author = {Yu{-}Hsuan Lee and
Yu{-}Hsing Chiu and
Szu{-}Hsuan Lai and
Wen{-}Yu Chiou and
Yue{-}Fang Kuo},
title = {A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression
Engine for Video Coding Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1119--1132},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3175889},
doi = {10.1109/TVLSI.2022.3175889},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeCLCK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLUHP22,
author = {Inho Lee and
Yangki Lee and
Hongjun Um and
Seongmin Hong and
Yongjun Park},
title = {Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1461--1472},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3178615},
doi = {10.1109/TVLSI.2022.3178615},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLUHP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeYSK22,
author = {Hayoung Lee and
Younwoo Yoo and
Seung Ho Shin and
Sungho Kang},
title = {{ECMO:} {ECC} Architecture Reusing Content-Addressable Memories for
Obtaining High Reliability in {DRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {781--793},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3153894},
doi = {10.1109/TVLSI.2022.3153894},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeYSK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LempelBS22,
author = {Yosef Lempel and
Rinat Breuer and
Joseph Shor},
title = {A 700-{\(\mu\)}m{\({^2}\)}, Ring-Oscillator-Based Thermal Sensor in
16-nm FinFET},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {248--252},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3137338},
doi = {10.1109/TVLSI.2021.3137338},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LempelBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiPY22,
author = {Dai Li and
Akhil Reddy Pakala and
Kaiyuan Yang},
title = {MeNTT: {A} Compact and Efficient Processing-in-Memory Number Theoretic
Transform {(NTT)} Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {579--588},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151321},
doi = {10.1109/TVLSI.2022.3151321},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiPY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWJSJM22,
author = {Shengzhao Li and
Qin Wang and
Jianfei Jiang and
Weiguang Sheng and
Naifeng Jing and
Zhigang Mao},
title = {An Efficient {CNN} Accelerator Using Inter-Frame Data Reuse of Videos
on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1587--1600},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151788},
doi = {10.1109/TVLSI.2022.3151788},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWJSJM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWZHL22,
author = {Yuyang Li and
Yawen Wu and
Xincheng Zhang and
Jingtong Hu and
Inhee Lee},
title = {Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation
for a Millimeter-Scale Sensing System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {849--859},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3171308},
doi = {10.1109/TVLSI.2022.3171308},
timestamp = {Thu, 14 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWZHL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZWSZ22,
author = {Dengquan Li and
Lei Zhao and
Longsheng Wang and
Yi Shen and
Zhangming Zhu},
title = {A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved
ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1558--1562},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3189641},
doi = {10.1109/TVLSI.2022.3189641},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZWSZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZZLGTW22,
author = {Zhen Li and
Su Zheng and
Jide Zhang and
Yao Lu and
Jingbo Gao and
Jun Tao and
Lingli Wang},
title = {Adaptable Approximate Multiplier Design Based on Input Distribution
and Polarity},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1813--1826},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3197229},
doi = {10.1109/TVLSI.2022.3197229},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZZLGTW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZZLJ22,
author = {Yao Li and
Bo Zhou and
Fuyuan Zhao and
Yujie Liu and
Yeran Jin},
title = {A 1.15-mW Low-Power Low-Complexity Reconfigurable {FM-UWB} Transmitter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {706--719},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151336},
doi = {10.1109/TVLSI.2022.3151336},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZZLJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LianRCCLCMM22,
author = {Wen Xun Lian and
Harikrishnan Ramiah and
Gabriel Chong and
Kishore Kumar Pakkirisami Churchill and
Nai Shyan Lai and
Yong Chen and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A -20-dBm Sensitivity {RF} Energy-Harvesting Rectifier Front End Using
a Transformer {IMN}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1808--1812},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3207158},
doi = {10.1109/TVLSI.2022.3207158},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LianRCCLCMM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangWH22,
author = {Aaron C.{-}W. Liang and
Charles H.{-}P. Wen and
Hsuan{-}Ming Huang},
title = {A General and Automatic Cell Layout Generation Framework With Implicit
Learning on Design Rules},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1341--1354},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3179527},
doi = {10.1109/TVLSI.2022.3179527},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangWH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiaoZ22,
author = {Tuotian Liao and
Lihong Zhang},
title = {High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware
Analog {IC} Sizing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {15--28},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3102088},
doi = {10.1109/TVLSI.2021.3102088},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiaoZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinPSVCLB22,
author = {Hesheng Lin and
Geert Van der Plas and
Xiao Sun and
Dimitrios Velenis and
Francky Catthoor and
Rudy Lauwereins and
Eric Beyne},
title = {Efficient Backside Power Delivery for High-Performance Computing Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1748--1756},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3183904},
doi = {10.1109/TVLSI.2022.3183904},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinPSVCLB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinVNSCLPB22,
author = {Hesheng Lin and
Dimitrios Velenis and
Philip Nolmans and
Xiao Sun and
Francky Catthoor and
Rudy Lauwereins and
Geert Van der Plas and
Eric Beyne},
title = {84{\%}-Efficiency Fully Integrated Voltage Regulator for Computing
Systems Enabled by 2.5-D High-Density {MIM} Capacitor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {661--665},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3149589},
doi = {10.1109/TVLSI.2022.3149589},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinVNSCLPB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinWMSC22,
author = {Ji{-}Yung Lin and
Pieter Weckx and
Subrat Mishra and
Alessio Spessot and
Francky Catthoor},
title = {Multitimescale Mitigation for Performance Variability Improvement
in Time-Critical Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1757--1769},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3177861},
doi = {10.1109/TVLSI.2022.3177861},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinWMSC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinZTCLT22,
author = {Jai{-}Ming Lin and
Liang{-}Chi Zane and
Min{-}Chia Tsai and
Yung{-}Chen Chen and
Che{-}Li Lin and
Chen{-}Fa Tsai},
title = {{PPOM:} An Effective Post-Global Placement Optimization Methodology
for Better Wirelength and Routability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1783--1793},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3201946},
doi = {10.1109/TVLSI.2022.3201946},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinZTCLT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuC22,
author = {Mengyun Liu and
Krishnendu Chakrabarty},
title = {Online Fault Detection in ReRAM-Based Computing Systems for Inferencing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {392--405},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3139530},
doi = {10.1109/TVLSI.2021.3139530},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuJLQL22,
author = {Lianxi Liu and
Yaling Ji and
Xufeng Liao and
Zhenghe Qin and
Hongzhi Liang},
title = {A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump {PLL} With High Spectrum Purity},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {113--122},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3140457},
doi = {10.1109/TVLSI.2022.3140457},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuJLQL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuL22,
author = {Xiaolong Liu and
Howard C. Luong},
title = {Analysis and Design of Magnetically Tuned {W} -Band Oscillators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {732--743},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3159030},
doi = {10.1109/TVLSI.2022.3159030},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuZJJXZZ22,
author = {Zhongyang Liu and
Haineng Zhang and
Jianwei Jiang and
Yanjie Jia and
Yuqiao Xie and
Shichang Zou and
Zhengxuan Zhang},
title = {A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets
Resilient Latch Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1867--1877},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3204827},
doi = {10.1109/TVLSI.2022.3204827},
timestamp = {Sat, 02 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuZJJXZZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuHW22,
author = {Jinming Lu and
Jian Huang and
Zhongfeng Wang},
title = {{THETA:} {A} High-Efficiency Training Accelerator for DNNs With Triple-Side
Sparsity Exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1034--1046},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3175582},
doi = {10.1109/TVLSI.2022.3175582},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuHW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuSFE22,
author = {Hsi{-}Hung Lu and
Chung{-}An Shen and
Mohammed E. Fouda and
Ahmed M. Eltawil},
title = {Configurable Independent Component Analysis Preprocessing Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1840--1852},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3209538},
doi = {10.1109/TVLSI.2022.3209538},
timestamp = {Sun, 12 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuSFE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LyuXCWLW22,
author = {Fei Lyu and
Yan Xia and
Yuheng Chen and
Yanxu Wang and
Yuanyong Luo and
Yu Wang},
title = {High-Throughput Low-Latency Pipelined Divider for Single-Precision
Floating-Point Numbers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {544--548},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3147946},
doi = {10.1109/TVLSI.2022.3147946},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LyuXCWLW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaZXCYNLNYL22,
author = {Xiaoyang Ma and
Hongtao Zhong and
Nuo Xiu and
Yiming Chen and
Guodong Yin and
Vijaykrishnan Narayanan and
Yongpan Liu and
Kai Ni and
Huazhong Yang and
Xueqing Li},
title = {CapCAM: {A} Multilevel Capacitive Content Addressable Memory for High-Accuracy
and High-Scalability Search and Compute Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1770--1782},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3198492},
doi = {10.1109/TVLSI.2022.3198492},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaZXCYNLNYL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MachaRIR22,
author = {Naveen Kumar Macha and
Bhavana Tejaswini Repalle and
Md Arif Iqbal and
Mostafizur Rahman},
title = {Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1073--1083},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3173344},
doi = {10.1109/TVLSI.2022.3173344},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MachaRIR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaoDLCWDLHY22,
author = {Wei Mao and
Liuyao Dai and
Kai Li and
Quan Cheng and
Yuhang Wang and
Laimin Du and
Shaobo Luo and
Mingqiang Huang and
Hao Yu},
title = {An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized
Deep Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1878--1890},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3210069},
doi = {10.1109/TVLSI.2022.3210069},
timestamp = {Mon, 16 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaoDLCWDLHY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaoLCDLXLLY22,
author = {Wei Mao and
Kai Li and
Quan Cheng and
Liuyao Dai and
Boyu Li and
Xinang Xie and
He Li and
Longyang Lin and
Hao Yu},
title = {A Configurable Floating-Point Multiple-Precision Processing Element
for {HPC} and {AI} Converged Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {213--226},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3128435},
doi = {10.1109/TVLSI.2021.3128435},
timestamp = {Mon, 16 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaoLCDLXLLY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaragkoudakiTP22,
author = {Eleni Maragkoudaki and
William B. Toms and
Vasilis F. Pavlidis},
title = {Energy-Efficient Encoding for High-Speed Serial Interfaces},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1484--1496},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3194256},
doi = {10.1109/TVLSI.2022.3194256},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaragkoudakiTP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoghadasPS22,
author = {Seyed Hamidreza Moghadas and
Michael Pehl and
Georg Sigl},
title = {{ROPAD:} Enhancing the Digital Ring Oscillator Probing Attempt Detector
for Protecting Irregular Data Buses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1716--1727},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3191471},
doi = {10.1109/TVLSI.2022.3191471},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoghadasPS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NagataMM22,
author = {Makoto Nagata and
Takuji Miki and
Noriyuki Miura},
title = {Physical Attack Protection Techniques for {IC} Chip Level Hardware
Security},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {5--14},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3073946},
doi = {10.1109/TVLSI.2021.3073946},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NagataMM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NairNCT22,
author = {Abhishek Ramdas Nair and
Pallab Kumar Nath and
Shantanu Chakrabartty and
Chetan Singh Thakur},
title = {Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1601--1614},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3189780},
doi = {10.1109/TVLSI.2022.3189780},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NairNCT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NannipieriMBCZS22,
author = {Pietro Nannipieri and
Stefano Di Matteo and
Luca Baldanzi and
Luca Crocetti and
Luca Zulberti and
Sergio Saponara and
Luca Fanucci},
title = {{VLSI} Design of Advanced-Features {AES} Cryptoprocessor in the Framework
of the European Processor Initiative},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {177--186},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3129107},
doi = {10.1109/TVLSI.2021.3129107},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NannipieriMBCZS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NasiriLZ22,
author = {Hamed Nasiri and
Cheng Li and
Lihong Zhang},
title = {Ultra-Low Power {SAR} {ADC} Using Statistical Characteristics of Low-Activity
Signals},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1319--1331},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3187659},
doi = {10.1109/TVLSI.2022.3187659},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NasiriLZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NathK22,
author = {Arijit Nath and
Hemangee K. Kapoor},
title = {Pop-Crypt: Identification and Management of Popular Words for Enhancing
Lifetime of EnCrypted Nonvolatile Main Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1219--1229},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3183793},
doi = {10.1109/TVLSI.2022.3183793},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NathK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NathRBR22,
author = {Atul Prasad Deb Nath and
Kshitij Raj and
Swarup Bhunia and
Sandip Ray},
title = {SoCCom: Automated Synthesis of System-on-Chip Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {449--462},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3141326},
doi = {10.1109/TVLSI.2022.3141326},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NathRBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NgCCCG22,
author = {Jun{-}Sheng Ng and
Juncheng Chen and
Kwen{-}Siong Chong and
Joseph S. Chang and
Bah{-}Hwee Gwee},
title = {A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic {AES} Accelerator
Against Side-Channel Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1144--1157},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3175180},
doi = {10.1109/TVLSI.2022.3175180},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NgCCCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NiKOL22,
author = {Ziying Ni and
Dur{-}e{-}Shahwar Kundi and
M{\'{a}}ire O'Neill and
Weiqiang Liu},
title = {A High-Performance {SIKE} Hardware Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {803--815},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3152011},
doi = {10.1109/TVLSI.2022.3152011},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NiKOL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NigussieSLMPF22,
author = {Theodros Nigussie and
Joshua Schabel and
Steve Lipa and
Lisa G. McIlrath and
Robert Patti and
Paul D. Franzon},
title = {Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1230--1243},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3179304},
doi = {10.1109/TVLSI.2022.3179304},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NigussieSLMPF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OzceylanHGG22,
author = {Baver Ozceylan and
Boudewijn R. Haverkort and
Maurits de Graaf and
Marco E. T. Gerards},
title = {Minimizing the Maximum Processor Temperature by Temperature-Aware
Scheduling of Real-Time Tasks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1084--1097},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3160601},
doi = {10.1109/TVLSI.2022.3160601},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/OzceylanHGG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkJ22,
author = {Youngmin Park and
Dongsuk Jeon},
title = {A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free {LDO} With
0.15-1.15V Output Range and 0.183-fs FoM},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1269--1280},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3180774},
doi = {10.1109/TVLSI.2022.3180774},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkJ22a,
author = {Hyunho Park and
Hanwool Jeong},
title = {Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1728--1738},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3184410},
doi = {10.1109/TVLSI.2022.3184410},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkJ22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PearceSKTKK22,
author = {Hammond Pearce and
Virinchi Roy Surabhi and
Prashanth Krishnamurthy and
Joshua Trujillo and
Ramesh Karri and
Farshad Khorrami},
title = {Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {926--937},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3171174},
doi = {10.1109/TVLSI.2022.3171174},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PearceSKTKK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PentapatiL22,
author = {Sai Pentapati and
Sung Kyu Lim},
title = {Metal Layer Sharing: {A} Routing Optimization Technique for Monolithic
3D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1355--1367},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3181185},
doi = {10.1109/TVLSI.2022.3181185},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PentapatiL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz22,
author = {Irith Pomeranz},
title = {Preponing Fault Detections for Test Compaction Under Transparent Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1543--1547},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3189804},
doi = {10.1109/TVLSI.2022.3189804},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz22a,
author = {Irith Pomeranz},
title = {Test Sequences for Faults in the Scan Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1568--1572},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3182540},
doi = {10.1109/TVLSI.2022.3182540},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz22b,
author = {Irith Pomeranz},
title = {Functional Test Sequences as a Source for Partially Functional Launch-on-Shift
Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1803--1807},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3198523},
doi = {10.1109/TVLSI.2022.3198523},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz22b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PundirPFT22,
author = {Nitin Pundir and
Jungmin Park and
Farimah Farahmandi and
Mark M. Tehranipoor},
title = {Power Side-Channel Leakage Assessment Framework at Register-Transfer
Level},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1207--1218},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3175067},
doi = {10.1109/TVLSI.2022.3175067},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PundirPFT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QiuZCX22,
author = {Feng Qiu and
Haoshen Zhu and
Wenquan Che and
Quan Xue},
title = {A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure
and High Voltage Gain},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {966--974},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3152169},
doi = {10.1109/TVLSI.2022.3152169},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QiuZCX22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QueNNBFZMTNL22,
author = {Zhiqiang Que and
Hiroki Nakahara and
Eriko Nurvitadhi and
Andrew Boutros and
Hongxiang Fan and
Chenglong Zeng and
Jiuxi Meng and
Kuen Hung Tsoi and
Xinyu Niu and
Wayne Luk},
title = {Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication
on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {227--237},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3135353},
doi = {10.1109/TVLSI.2021.3135353},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QueNNBFZMTNL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RavipatiKSHPA22,
author = {Divya Praneetha Ravipati and
Rajesh Kedia and
Victor M. van Santen and
J{\"{o}}rg Henkel and
Preeti Ranjan Panda and
Hussam Amrouch},
title = {{FN-CACTI:} Advanced {CACTI} for FinFET and NC-FinFET Technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {339--352},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3123112},
doi = {10.1109/TVLSI.2021.3123112},
timestamp = {Wed, 27 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RavipatiKSHPA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReisGNH22,
author = {Dayane Reis and
Haoran Geng and
Michael T. Niemier and
Xiaobo Sharon Hu},
title = {{IMCRYPTO:} An In-Memory Computing Fabric for {AES} Encryption and
Decryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {553--565},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3157270},
doi = {10.1109/TVLSI.2022.3157270},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ReisGNH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Salmani22,
author = {Hassan Salmani},
title = {Gradual-N-Justification {(GNJ)} to Reduce False-Positive Hardware
Trojan Detection in Gate-Level Netlist},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {515--525},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3143349},
doi = {10.1109/TVLSI.2022.3143349},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Salmani22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SamantaS22,
author = {Smrutilekha Samanta and
Santanu Sarkar},
title = {A Pairwise Swap Enabled Randomized {DEM} Addressing Intersegment Mismatch
for Current Steering Digital-to-Analog Converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1332--1340},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3183353},
doi = {10.1109/TVLSI.2022.3183353},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SamantaS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaragadaD22,
author = {Prasanna Kumar Saragada and
Bishnu Prasad Das},
title = {In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based
Compact Thermometric Code},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1473--1483},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3199396},
doi = {10.1109/TVLSI.2022.3199396},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SaragadaD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarkerKA22,
author = {Ausmita Sarker and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Efficient Error Detection Architectures for Postquantum Signature
Falcon's Sampler and {KEM} {SABER}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {794--802},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3156479},
doi = {10.1109/TVLSI.2022.3156479},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SarkerKA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShamsN22,
author = {Nakisa Shams and
Frederic Nabki},
title = {Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic
Selection {RF} Receiver Front-End Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {253--266},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3142235},
doi = {10.1109/TVLSI.2022.3142235},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShamsN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SharmaSS22,
author = {Rahul Sharma and
Rahul Shrestha and
Satinder K. Sharma},
title = {Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues
and Eigenvectors Using CORDIC-Based Parallel Jacobi Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1020--1033},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3170526},
doi = {10.1109/TVLSI.2022.3170526},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SharmaSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShuklaMITFT22,
author = {Priyesh Shukla and
Ankith Muralidhar and
Nick Iliev and
Theja Tulabandhula and
Sawyer B. Fuller and
Amit Ranjan Trivedi},
title = {Ultralow-Power Localization of Insect-Scale Drones: Interplay of Probabilistic
Filtering and Compute-in-Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {68--80},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3100252},
doi = {10.1109/TVLSI.2021.3100252},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShuklaMITFT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghalH22,
author = {Naina Singhal and
S. M. Rezaul Hasan},
title = {A 25-30-GHz {RMS} Error-Minimized 360{\textdegree} Continuous Analog
Phase Shifter Using Closed-Loop Self-Tuning {I/Q} Generator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {720--731},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3162893},
doi = {10.1109/TVLSI.2022.3162893},
timestamp = {Thu, 02 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghalH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SistoZCKXMWHR22,
author = {Giuliano Sisto and
Odysseas Zografos and
Bilal Chehab and
Naveen Kakarla and
Yang Xiang and
Dragomir Milojevic and
Pieter Weckx and
Geert Hellings and
Julien Ryckaert},
title = {Evaluation of Nanosheet and Forksheet Width Modulation for Digital
{IC} Design in the Sub-3-nm Era},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1497--1506},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3190080},
doi = {10.1109/TVLSI.2022.3190080},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SistoZCKXMWHR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SomappaB22,
author = {Laxmeesha Somappa and
Maryam Shojaei Baghini},
title = {Continuous-Time Hybrid {\(\Delta\)}{\(\Sigma\)} Modulators for Sub-{\(\mu\)}W
Power Multichannel Biomedical Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {406--417},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3140222},
doi = {10.1109/TVLSI.2022.3140222},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SomappaB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongCW22,
author = {Suwen Song and
Hangxuan Cui and
Zhongfeng Wang},
title = {A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic
{LDPC} Decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1553--1557},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3190317},
doi = {10.1109/TVLSI.2022.3190317},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SongCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SravaniS22,
author = {Mesala M. Sravani and
Ananiah Durai Sundararajan},
title = {On Efficiency Enhancement of {SHA-3} for FPGA-Based Multimodal Biometric
Authentication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {488--501},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3148275},
doi = {10.1109/TVLSI.2022.3148275},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SravaniS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StangherlinS22,
author = {Kleber Stangherlin and
Manoj Sachdev},
title = {Design and Implementation of a Secure {RISC-V} Microprocessor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1705--1715},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3203307},
doi = {10.1109/TVLSI.2022.3203307},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/StangherlinS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SuYYYL22,
author = {Yang Su and
Bai{-}Long Yang and
Chen Yang and
Zepeng Yang and
Yi{-}Wei Liu},
title = {A Highly Unified Reconfigurable Multicore Architecture to Speed Up
{NTT/INTT} for Homomorphic Polynomial Multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {993--1006},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3166355},
doi = {10.1109/TVLSI.2022.3166355},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SuYYYL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TaheriM22,
author = {Hamidreza Esmaeili Taheri and
Mitra Mirhassani},
title = {A Pre-Activation, Golden {IC} Free, Hardware Trojan Detection Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {315--324},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3138303},
doi = {10.1109/TVLSI.2021.3138303},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TaheriM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TanSI22,
author = {Yi Tan and
Yohsuke Shiiki and
Hiroki Ishikuro},
title = {Optimization of Gate Voltage in Capacitive {DC-DC} Converters for
Thermoelectric Energy Harvesting},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {463--473},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3141909},
doi = {10.1109/TVLSI.2022.3141909},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TanSI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TaoRCR22,
author = {Chun Tao and
Deboleena Roy and
Indranil Chakraborty and
Kaushik Roy},
title = {On Noise Stability and Robustness of Adversarially Trained Networks
on {NVM} Crossbars},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1448--1460},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3193312},
doi = {10.1109/TVLSI.2022.3193312},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TaoRCR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TavakoliBY22,
author = {Erfan Bank Tavakoli and
Amir Beygi and
Xuebin Yao},
title = {RPkNN: An OpenCL-Based {FPGA} Implementation of the Dimensionality-Reduced
kNN Algorithm Using Random Projection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {549--552},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3147743},
doi = {10.1109/TVLSI.2022.3147743},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TavakoliBY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThirumalaRGR22,
author = {Sandeep Krishna Thirumala and
Arnab Raha and
Sumeet Gupta and
Vijay Raghunathan},
title = {Exploring the Design of Energy-Efficient Intermittently Powered Systems
Using Reconfigurable Ferroelectric Transistors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {365--378},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3125248},
doi = {10.1109/TVLSI.2021.3125248},
timestamp = {Mon, 15 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ThirumalaRGR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThirumoorthiHMK22,
author = {Madhan Thirumoorthi and
Moslem Heidarpur and
Mitra Mirhassani and
Mohammed A. S. Khalid},
title = {An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for
Finite Field Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {603--614},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3148207},
doi = {10.1109/TVLSI.2022.3148207},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ThirumoorthiHMK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TongLW22,
author = {Xingyuan Tong and
Dong Liu and
Ronghua Wang},
title = {A 12-Bit Current-Steering {DAC} With Unary- Splitting -Binary Segmented
Architecture and Improved Decoding Circuit Topology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1391--1400},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3200946},
doi = {10.1109/TVLSI.2022.3200946},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TongLW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiL22,
author = {Yao{-}Hung Tsai and
Shen{-}Iuan Liu},
title = {A 0.0067-mm\({}^{\mbox{2}}\) 12-bit 20-MS/s {SAR} {ADC} Using Digital
Place-and-Route Tools in 40-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {905--914},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3170325},
doi = {10.1109/TVLSI.2022.3170325},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VenkateswarluMO22,
author = {Sankatali Venkateswarlu and
Subrat Mishra and
Herman Oprins and
Bjorn Vermeersch and
Moritz Brunion and
Jun{-}Han Han and
Mircea R. Stan and
Pieter Weckx and
Francky Catthoor},
title = {Thermal Performance Analysis of Mempool {RISC-V} Multicore SoC},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1668--1676},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3207553},
doi = {10.1109/TVLSI.2022.3207553},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VenkateswarluMO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WaliaTKDM22,
author = {Sumit Walia and
Bachu Varun Tej and
Arpita Kabra and
Joydeep Kumar Devnath and
Joycee Mekie},
title = {Fast and Low-Power Quantized Fixed Posit High-Accuracy {DNN} Implementation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {108--111},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3131609},
doi = {10.1109/TVLSI.2021.3131609},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WaliaTKDM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangSHZRLS22,
author = {Xuecheng Wang and
Yahao Song and
Fengfan Hou and
Milin Zhang and
Andrew G. Richardson and
Timothy H. Lucas and
Jan Van der Spiegel},
title = {Design of a Real-Time Movement Decomposition-Based Rodent Tracker
and Behavioral Analyzer Based on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1133--1143},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3168783},
doi = {10.1109/TVLSI.2022.3168783},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangSHZRLS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangT22,
author = {Zhe{-}Yu Wang and
Pei{-}Yun Tsai},
title = {Design and Implementation of a 6.5-Gb/s Multiradix Simplified Viterbi-Sphere
Decoder for Trellis-Coded Generalized Spatial Modulation With Spatial
Multiplexing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1853--1866},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3200584},
doi = {10.1109/TVLSI.2022.3200584},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangWGCOL22,
author = {Yale Wang and
Chenghua Wang and
Chongyan Gu and
Yijun Cui and
M{\'{a}}ire O'Neill and
Weiqiang Liu},
title = {A Generic Dynamic Responding Mechanism and Secure Authentication Protocol
for Strong PUFs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1256--1268},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3189953},
doi = {10.1109/TVLSI.2022.3189953},
timestamp = {Wed, 22 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangWGCOL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZCG22,
author = {Tengfei Wang and
Chi Zhang and
Pei Cao and
Dawu Gu},
title = {Efficient Implementation of Dilithium Signature Scheme on {FPGA} SoC
Platform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1158--1171},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3179459},
doi = {10.1109/TVLSI.2022.3179459},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZLYJ22,
author = {Zhen Wang and
Guofa Zhang and
Peng Liu and
Jing Ye and
Jianhui Jiang},
title = {Accurate Reliability Boundary Evaluation of Approximate Arithmetic
Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1507--1518},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3193897},
doi = {10.1109/TVLSI.2022.3193897},
timestamp = {Mon, 22 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZLYJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangZYYY22,
author = {Fengjuan Wang and
Kai Zhang and
Xiangkun Yin and
Ningmei Yu and
Yuan Yang},
title = {A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band
Suppression Based on {TSV} Technology for W-Band Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {989--992},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3166746},
doi = {10.1109/TVLSI.2022.3166746},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangZYYY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WernerPZ22,
author = {Frank T. Werner and
Milos Prvulovic and
Alenka G. Zajic},
title = {Detection of Recycled ICs Using Backscattering Side-Channel Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1244--1255},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3190236},
doi = {10.1109/TVLSI.2022.3190236},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WernerPZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuKC22,
author = {Yue{-}Ming Wu and
Yu{-}Hsien Kao and
Ta{-}Shun Chu},
title = {A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved
Technique in 65-nm {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {29--39},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3124605},
doi = {10.1109/TVLSI.2021.3124605},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuKC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaoLCL22,
author = {Jinhai Xiao and
Ning Liang and
Bingwen Chen and
Maliang Liu},
title = {An 8.55-17.11-GHz {DDS} {FMCW} Chirp Synthesizer {PLL} Based on Double-Edge
Zero-Crossing Sampling {PD} With 51.7-fs\({}_{\mbox{rms}}\) Jitter
and Fast Frequency Hopping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {267--276},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3140206},
doi = {10.1109/TVLSI.2021.3140206},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaoLCL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XieTZ22,
author = {Zhenshan Xie and
Yok Jye Tang and
Xinmiao Zhang},
title = {Low-Latency Nested Decoding for Short Generalized Integrated Interleaved
{BCH} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1563--1567},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3179944},
doi = {10.1109/TVLSI.2022.3179944},
timestamp = {Mon, 11 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XieTZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiongDWZY22,
author = {Wei Xiong and
Gang Dong and
Yang Wang and
Zhangming Zhu and
Yintang Yang},
title = {3-D Compact Marchand Balun Design Based on Through-Silicon via Technology
for Monolithic and 3-D Integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1107--1118},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3170415},
doi = {10.1109/TVLSI.2022.3170415},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XiongDWZY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiongLLFC22,
author = {Botao Xiong and
Yukun Li and
Sicun Li and
Sheng Fan and
Yuchun Chang},
title = {Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic
and Antilogarithmic Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {243--247},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3136229},
doi = {10.1109/TVLSI.2021.3136229},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiongLLFC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuFLLWLL22,
author = {Dawen Xu and
Zhuangyu Feng and
Cheng Liu and
Li Li and
Ying Wang and
Huawei Li and
Xiaowei Li},
title = {Taming Process Variations in {CNFET} for Efficient Last-Level Cache
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {418--431},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3135502},
doi = {10.1109/TVLSI.2021.3135502},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuFLLWLL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuWHZHZ22,
author = {Dongdong Xu and
Xiang Wang and
Yuanchao Hao and
Zhun Zhang and
Qiang Hao and
Zhiyu Zhou},
title = {A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its
Hardware Implementation for IoT Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {8},
pages = {1007--1019},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3174205},
doi = {10.1109/TVLSI.2022.3174205},
timestamp = {Fri, 23 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XuWHZHZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuanK22,
author = {Zihao Xuan and
Yi Kang},
title = {High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1193--1206},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3179621},
doi = {10.1109/TVLSI.2022.3179621},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuanK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Yan22,
author = {Jin{-}Tai Yan},
title = {Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum
Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1519--1532},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3182290},
doi = {10.1109/TVLSI.2022.3182290},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Yan22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangCYMM22,
author = {Zunsong Yang and
Yong Chen and
Jia Yuan and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A 3.3-GHz Integer N-Type-II Sub-Sampling {PLL} Using a BFSK-Suppressed
Push-Pull {SS-PD} and a Fast-Locking {FLL} Achieving -82.2-dBc {REF}
Spur and -255-dB {FOM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {238--242},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3131219},
doi = {10.1109/TVLSI.2021.3131219},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangCYMM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangHCB22,
author = {Shuo Yang and
Tamzidul Hoque and
Prabuddha Chakraborty and
Swarup Bhunia},
title = {Golden-Free Hardware Trojan Detection Using Self-Referencing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {325--338},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3140250},
doi = {10.1109/TVLSI.2022.3140250},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangHCB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangMHXM22,
author = {Chen Yang and
Yishuo Meng and
Kaibo Huo and
Jiawei Xi and
Kuizhi Mei},
title = {A Sparse {CNN} Accelerator for Eliminating Redundant Computations
in Intra- and Inter-Convolutional/Pooling Layers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1902--1915},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3211665},
doi = {10.1109/TVLSI.2022.3211665},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangMHXM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YaoZYZZ22,
author = {Rui Yao and
Yinhua Zhao and
Yongchuan Yu and
Yihe Zhao and
Xueyan Zhong},
title = {Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks
on Modern Heterogeneous FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {474--487},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151402},
doi = {10.1109/TVLSI.2022.3151402},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YaoZYZZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YasaeiFF22,
author = {Rozhin Yasaei and
Sina Faezi and
Mohammad Abdullah Al Faruque},
title = {Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional
Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1401--1411},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3191683},
doi = {10.1109/TVLSI.2022.3191683},
timestamp = {Tue, 18 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YasaeiFF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YoonJSHCKKB22,
author = {Dong{-}Hyun Yoon and
Dong{-}Kyu Jung and
Kiho Seong and
Jae{-}Soub Han and
Keun{-}Yong Chung and
Ju Eon Kim and
Tony Tae{-}Hyoung Kim and
Kwang{-}Hyun Baek},
title = {A 3.2-GHz 178-fs\({}_{\mbox{rms}}\) Jitter Subsampling PLL/DLL-Based
Injection-Locked Clock Multiplier},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {7},
pages = {915--925},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3169636},
doi = {10.1109/TVLSI.2022.3169636},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YoonJSHCKKB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuCZZLWYK22,
author = {Yiming Yu and
Dong Chen and
Xiaoning Zhang and
Chenxi Zhao and
Huihua Liu and
Yunqiu Wu and
Wen{-}Yan Yin and
Kai Kang},
title = {A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test
Capability in 180-nm {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {694--705},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151383},
doi = {10.1109/TVLSI.2022.3151383},
timestamp = {Fri, 03 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuCZZLWYK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZafarASJ22,
author = {Mubeen Zafar and
Muhammad Naeem Awais and
Muhammad Naeem Shehzad and
Abbas Javed},
title = {{CEVGMM:} Computationally Efficient Versatile Generic Memristor Model},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1794--1802},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3194251},
doi = {10.1109/TVLSI.2022.3194251},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZafarASJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangDPLFJ22,
author = {Ying Zhang and
Yi Ding and
Zebo Peng and
Huawei Li and
Masahiro Fujita and
Jianhui Jiang},
title = {BMC-Based Temperature-Aware {SBST} for Worst-Case Delay Fault Testing
Under High Temperature},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1677--1690},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3186946},
doi = {10.1109/TVLSI.2022.3186946},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangDPLFJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangDZ22,
author = {Weidong Zhang and
Zhenxing Dong and
Yan Zhu},
title = {EddySuperblock: Improving {NAND} Flash Efficiency and Lifetime by
Endurance-Driven Dynamic Superblock Management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {1},
pages = {95--107},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3126862},
doi = {10.1109/TVLSI.2021.3126862},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangDZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangHXWXFS22,
author = {Yewei Zhang and
Kejie Huang and
Rui Xiao and
Bo Wang and
Yanfeng Xu and
Jicong Fan and
Haibin Shen},
title = {An 8-Bit in Resistive Memory Computing Core With Regulated Passive
Neuron and Bitline Weight Mapping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {4},
pages = {379--391},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3140395},
doi = {10.1109/TVLSI.2022.3140395},
timestamp = {Thu, 20 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangHXWXFS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangNZLWY22,
author = {Qihui Zhang and
Ning Ning and
Zhong Zhang and
Jing Li and
Kejun Wu and
Qi Yu},
title = {A 12-Bit Two-Step Single-Slope {ADC} With a Constant Input-Common-Mode
Level Resistor Ramp Generator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {644--655},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3156612},
doi = {10.1109/TVLSI.2022.3156612},
timestamp = {Wed, 18 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangNZLWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangWLJCMZZ22,
author = {Hanrui Zhang and
Xiaofei Wang and
Nannan Li and
Zihao Jiao and
Liang Chen and
Di Mu and
Jie Zhang and
Hong Zhang},
title = {A 2.5-MHz BW, 75-dB {SNDR} Noise-Shaping {SAR} {ADC} With a 1st-Order
Hybrid {EF-CIFF} Structure Assisted by Unity-Gain Buffer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {12},
pages = {1928--1932},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3213365},
doi = {10.1109/TVLSI.2022.3213365},
timestamp = {Wed, 25 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangWLJCMZZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangYZLWN22,
author = {Zhong Zhang and
Qi Yu and
Qihui Zhang and
Jing Li and
Kejun Wu and
Ning Ning},
title = {A Code-Recombination Algorithm-Based {ADC} With Feature Extraction
for {WBSN} Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {2},
pages = {134--142},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3128166},
doi = {10.1109/TVLSI.2021.3128166},
timestamp = {Wed, 23 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangYZLWN22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoLWZLPTC22,
author = {Yue Zhao and
Zhiting Lin and
Xiulong Wu and
Qiang Zhao and
Wenjuan Lu and
Chunyu Peng and
Zhongzhen Tong and
Junning Chen},
title = {Configurable Memory With a Multilevel Shared Structure Enabling In-Memory
Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {5},
pages = {566--578},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3148327},
doi = {10.1109/TVLSI.2022.3148327},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoLWZLPTC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuQPLD22,
author = {Xiaorui Zhu and
Yihan Qian and
Zhixiang Peng and
Yimin Liang and
Shengxi Diao},
title = {Analysis and Design of a DC-12-GHz Distribution Power Amplifier for
Quantum Key Distribution Application},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1306--1318},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3180503},
doi = {10.1109/TVLSI.2022.3180503},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuQPLD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZokaeiTE22,
author = {Abolfazl Zokaei and
Dmitri V. Truhachev and
Kamal El{-}Sankary},
title = {Memory Optimized Hardware Implementation of Open {FEC} Encoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {10},
pages = {1548--1552},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3180554},
doi = {10.1109/TVLSI.2022.3180554},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZokaeiTE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Zolfagharinejad22,
author = {Mohamadreza Zolfagharinejad and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {Posit Process Element for Using in Energy-Efficient {DNN} Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {6},
pages = {844--848},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3165510},
doi = {10.1109/TVLSI.2022.3165510},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Zolfagharinejad22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0002J021,
author = {Abhijit Das and
John Jose and
Prabhat Mishra},
title = {Data Criticality in Multithreaded Applications: An Insight for Many-Core
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1675--1679},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3092218},
doi = {10.1109/TVLSI.2021.3092218},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/0002J021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AkbariHHT21,
author = {Meysam Akbari and
Safwan Mawlood Hussein and
Yasir Hashim and
Kea{-}Tiong Tang},
title = {An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1601--1611},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3084695},
doi = {10.1109/TVLSI.2021.3084695},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AkbariHHT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlanGH21,
author = {Tanfer Alan and
Andreas Gerstlauer and
J{\"{o}}rg Henkel},
title = {Cross-Layer Approximate Hardware Synthesis for Runtime Configurable
Accuracy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1231--1243},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3068312},
doi = {10.1109/TVLSI.2021.3068312},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AlanGH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlaqlRB21,
author = {Abdulrahman Alaql and
Md. Moshiur Rahman and
Swarup Bhunia},
title = {{SCOPE:} Synthesis-Based Constant Propagation Attack on Logic Locking},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1529--1542},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3089555},
doi = {10.1109/TVLSI.2021.3089555},
timestamp = {Wed, 06 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlaqlRB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto21,
author = {Massimo Alioto},
title = {Opening of the 2021 Editorial Year - Overture for a New Year of Change},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {1--2},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3045820},
doi = {10.1109/TVLSI.2020.3045820},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto21a,
author = {Massimo Alioto},
title = {Second Quarter of the 2021 Editorial Year - {A} Year in Crescendo},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {815--842},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3065344},
doi = {10.1109/TVLSI.2021.3065344},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AljuffriZRHT21,
author = {Abdullah Aljuffri and
Marc Zwalua and
Cezar Rodolfo Wedig Reinbrecht and
Said Hamdioui and
Mottaqiallah Taouil},
title = {Applying Thermal Side-Channel Attacks on Asymmetric Cryptography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1930--1942},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3111407},
doi = {10.1109/TVLSI.2021.3111407},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AljuffriZRHT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AlnuayriKMR21,
author = {Turki Alnuayri and
S. Saqib Khursheed and
Antonio Leonel Hern{\'{a}}ndez Mart{\'{\i}}nez and
Daniele Rossi},
title = {Differential Aging Sensor Using Subthreshold Leakage Current to Detect
Recycled ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2064--2075},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3115247},
doi = {10.1109/TVLSI.2021.3115247},
timestamp = {Sat, 25 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AlnuayriKMR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AmiranyJM21,
author = {Abdolah Amirany and
Kian Jafari and
Mohammad Hossein Moaiyeri},
title = {High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal
Shift Register},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {916--924},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3055983},
doi = {10.1109/TVLSI.2021.3055983},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AmiranyJM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AntoniadisES21,
author = {Charalampos Antoniadis and
Nestor E. Evmorfopoulos and
Georgios I. Stamoulis},
title = {Graph-Based Sparsification and Synthesis of Dense Matrices in the
Reduction of {RLC} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {580--590},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3049628},
doi = {10.1109/TVLSI.2021.3049628},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AntoniadisES21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ArdesiTGP21,
author = {Yuri Ardesi and
Giovanna Turvani and
Mariagrazia Graziano and
Gianluca Piccinini},
title = {{SCERPA} Simulation of Clocked Molecular Field-Coupling Nanocomputing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {558--567},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3045198},
doi = {10.1109/TVLSI.2020.3045198},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ArdesiTGP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ArkaJDPC21,
author = {Aqeeb Iqbal Arka and
Biresh Kumar Joardar and
Janardhan Rao Doppa and
Partha Pratim Pande and
Krishnendu Chakrabarty},
title = {Performance and Accuracy Tradeoffs for Training Graph Neural Networks
on ReRAM-Based Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1743--1756},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3110721},
doi = {10.1109/TVLSI.2021.3110721},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ArkaJDPC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AryaPS21,
author = {Neelam Arya and
Manisha Pattanaik and
G. K. Sharma},
title = {Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1994--1997},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3114616},
doi = {10.1109/TVLSI.2021.3114616},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AryaPS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzarKRHSS21,
author = {Kimia Zamiri Azar and
Hadi Mardani Kamali and
Shervin Roshanisefat and
Houman Homayoun and
Christos P. Sotiriou and
Avesta Sasan},
title = {Data Flow Obfuscation: {A} New Paradigm for Obfuscating Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {643--656},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3060345},
doi = {10.1109/TVLSI.2021.3060345},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AzarKRHSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AzimiSS21,
author = {Sarah Azimi and
Corrado De Sio and
Luca Sterpone},
title = {A Radiation-Hardened {CMOS} Full-Adder Based on Layout Selective Transistor
Duplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1596--1600},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3086897},
doi = {10.1109/TVLSI.2021.3086897},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AzimiSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BahadoriJN21,
author = {Milad Bahadori and
Kimmo J{\"{a}}rvinen and
Valtteri Niemi},
title = {{FPGA} Implementations of 256-Bit {SNOW} Stream Ciphers for Postquantum
Mobile Security},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1943--1954},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3108430},
doi = {10.1109/TVLSI.2021.3108430},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BahadoriJN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BanerjeeCNC21,
author = {Sanmitra Banerjee and
Arjun Chaudhuri and
August Ning and
Krishnendu Chakrabarty},
title = {Variation-Aware Delay Fault Testing for Carbon-Nanotube {FET} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {409--422},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3045417},
doi = {10.1109/TVLSI.2020.3045417},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BanerjeeCNC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaskaranS21,
author = {Saambhavi Baskaran and
Jack Sampson},
title = {Evaluation of Tradeoffs in the Design of {FPGA} Fabrics Using Electrostrictive
2-D FETs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {691--701},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3059979},
doi = {10.1109/TVLSI.2021.3059979},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BaskaranS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BauerHICHRDEWUN21,
author = {Heiner Bauer and
Sebastian H{\"{o}}ppner and
Chris Paul Iatrou and
Zohra Charania and
Stephan Hartmann and
Saif{-}Ur Rehman and
Andreas Dixius and
Georg Ellguth and
Dennis Walter and
Johannes Uhlig and
Felix Neum{\"{a}}rker and
Marc Berthel and
Marco Stolba and
Florian Kelber and
Leon Urbas and
Christian Mayr},
title = {Hardware Implementation of an {OPC} {UA} Server for Industrial Field
Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1998--2002},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3117401},
doi = {10.1109/TVLSI.2021.3117401},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BauerHICHRDEWUN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Bhowmik21,
author = {Biswajit Bhowmik},
title = {Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip
Communication Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {1009--1021},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3059662},
doi = {10.1109/TVLSI.2021.3059662},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Bhowmik21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BoukhtacheBGB21,
author = {Seyfeddine Boukhtache and
Beno{\^{\i}}t Blaysat and
Michel Gr{\'{e}}diac and
Fran{\c{c}}ois Berry},
title = {Alternatives to Bicubic Interpolation Considering {FPGA} Hardware
Resource Consumption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {247--258},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3032888},
doi = {10.1109/TVLSI.2020.3032888},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BoukhtacheBGB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CantoKA21,
author = {Alvaro Cintas Canto and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Reliable CRC-Based Error Detection Constructions for Finite Field
Multipliers With Applications in Cryptography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {232--236},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3031170},
doi = {10.1109/TVLSI.2020.3031170},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CantoKA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CantoKA21a,
author = {Alvaro Cintas Canto and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {CRC-Based Error Detection Constructions for {FLT} and {ITA} Finite
Field Inversions Over GF(2\({}^{\mbox{m}}\))},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {1033--1037},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3061987},
doi = {10.1109/TVLSI.2021.3061987},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CantoKA21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoW21,
author = {Hongbo Cao and
Faqiang Wang},
title = {Spreading Operation Frequency Ranges of Memristor Emulators via a
New Sine-Based Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {617--630},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056472},
doi = {10.1109/TVLSI.2021.3056472},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CelikATL21,
author = {Firat Celik and
Ayca Akkaya and
Armin Tajalli and
Yusuf Leblebici},
title = {A 32-Gb/s {PAM-4} {SST} Transmitter With Four-Tap {FFE} Using High-Impedance
Driver in 28-nm {FDSOI}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1132--1140},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3068242},
doi = {10.1109/TVLSI.2021.3068242},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CelikATL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CenturelliSP21,
author = {Francesco Centurelli and
Giuseppe Scotti and
Gaetano Palumbo},
title = {A Very-Low-Voltage Frequency Divider in Folded {MOS} Current Mode
Logic With Complementary n- and p-type Flip-Flops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {998--1008},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3058730},
doi = {10.1109/TVLSI.2021.3058730},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CenturelliSP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabortyB21,
author = {Anirban Chakraborty and
Ayan Banerjee},
title = {CORDIC-Based High-Speed {VLSI} Architecture of Transform Model Estimation
for Real-Time Imaging},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {215--226},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3035514},
doi = {10.1109/TVLSI.2020.3035514},
timestamp = {Mon, 21 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChanLCJJ21,
author = {Hsun{-}Wei Chan and
Wei{-}Che Lee and
Kang{-}Lun Chiu and
Chih{-}Wei Jen and
Shyh{-}Jye Jou},
title = {A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking
Module for mmW Single Carrier Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {904--915},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3062050},
doi = {10.1109/TVLSI.2021.3062050},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChanLCJJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangZDCW21,
author = {Libo Chang and
Shengbing Zhang and
Huimin Du and
Yue Chen and
Shiyu Wang},
title = {A Reconfigurable Neural Network Processor With Tile-Grained Multicore
Pipeline for Object Detection on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1967--1980},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3109580},
doi = {10.1109/TVLSI.2021.3109580},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangZDCW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaurasiyaS21,
author = {Rohit B. Chaurasiya and
Rahul Shrestha},
title = {A New Hardware-Efficient Spectrum-Sensor {VLSI} Architecture for Data-Fusion-Based
Cooperative Cognitive-Radio Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {760--773},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3055344},
doi = {10.1109/TVLSI.2021.3055344},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaurasiyaS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHLLYL21,
author = {Kun{-}Chih Chen and
Ya{-}Wei Huang and
Geng{-}Ming Liu and
Jing{-}Wen Liang and
Yueh{-}Chi Yang and
Yuan{-}Hao Liao},
title = {A Hierarchical K-Means-Assisted Scenario-Aware Reconfigurable Convolutional
Neural Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {176--188},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3034351},
doi = {10.1109/TVLSI.2020.3034351},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHLLYL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHPH21,
author = {Qingkun Chen and
Wenjin Huang and
Yuze Peng and
Yihua Huang},
title = {A Reinforcement Learning-Based Framework for Solving the {IP} Mapping
Problem},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1638--1651},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3097712},
doi = {10.1109/TVLSI.2021.3097712},
timestamp = {Wed, 23 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHPH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHWLK21,
author = {Jiann{-}Jong Chen and
Yuh{-}Shyan Hwang and
Jyun{-}Heng Wu and
Chien{-}Hung Lai and
Yi{-}Tsen Ku},
title = {A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail
OTA-Based Current-Sensing Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1428--1436},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3071652},
doi = {10.1109/TVLSI.2021.3071652},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHWLK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHZH21,
author = {Qingkun Chen and
Wenjin Huang and
Yuanshan Zhang and
Yihua Huang},
title = {An {IP} Core Mapping Algorithm Based on Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {189--202},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3033658},
doi = {10.1109/TVLSI.2020.3033658},
timestamp = {Wed, 23 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHZH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLNGGC21,
author = {Jinbo Chen and
Chengcheng Lu and
Jiacheng Ni and
Xiaochen Guo and
Patrick Girard and
Yuanqing Cheng},
title = {{DOVA} {PRO:} {A} Dynamic Overwriting Voltage Adjustment Technique
for {STT-MRAM} {L1} Cache Considering Dielectric Breakdown Effect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1325--1334},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3073415},
doi = {10.1109/TVLSI.2021.3073415},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLNGGC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenZWLH21,
author = {Zhuojun Chen and
Judi Zhang and
Shuangchun Wen and
Ya Li and
Qinghui Hong},
title = {Competitive Neural Network Circuit Based on Winner-Take-All Mechanism
and Online Hebbian Learning Rule},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1095--1107},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3069221},
doi = {10.1109/TVLSI.2021.3069221},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenZWLH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengC21,
author = {Kuang{-}Wei Cheng and
Shih{-}En Chen},
title = {An Ultralow-Power {OOK/BFSK/DBPSK} Wake-Up Receiver Based on Injection-Locked
Oscillator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1379--1391},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3073166},
doi = {10.1109/TVLSI.2021.3073166},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengHLLP21,
author = {Chung{-}Kuan Cheng and
Chia{-}Tung Ho and
Daeyeal Lee and
Bill Lin and
Dongwon Park},
title = {Complementary-FET {(CFET)} Standard Cell Synthesis Framework for Design
and System Technology Co-Optimization Using {SMT}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1178--1191},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3065639},
doi = {10.1109/TVLSI.2021.3065639},
timestamp = {Mon, 01 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengHLLP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoiK21,
author = {Jaewon Choi and
Nam{-}Seog Kim},
title = {A Spurious and Oscillator Pulling Free {CMOS} Quadrature LO-Generator
for Cellular NB-IoT},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2098--2109},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3105819},
doi = {10.1109/TVLSI.2021.3105819},
timestamp = {Tue, 17 Sep 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoiK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoudhuryAG21,
author = {Rituparna Choudhury and
Shaik Rafi Ahamed and
Prithwijit Guha},
title = {Training Accelerator for Two Means Decision Tree},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1465--1469},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3076081},
doi = {10.1109/TVLSI.2021.3076081},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoudhuryAG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChuGWWLL21,
author = {Xiuqin Chu and
Wenting Guo and
Jun Wang and
Feng Wu and
Yuhuan Luo and
Yushan Li},
title = {Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear
High-Speed Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1370--1378},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3082208},
doi = {10.1109/TVLSI.2021.3082208},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChuGWWLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CollemanV21,
author = {Steven Colleman and
Marian Verhelst},
title = {High-Utilization, High-Flexibility Depth-First {CNN} Coprocessor for
Image Pixel Processing on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {461--471},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3046125},
doi = {10.1109/TVLSI.2020.3046125},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CollemanV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DasHSG21,
author = {Hritom Das and
Ali Ahmad Haidous and
Scott C. Smith and
Na Gong},
title = {Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1693--1706},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3098533},
doi = {10.1109/TVLSI.2021.3098533},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DasHSG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DasalukunteDLL21,
author = {Deepak Dasalukunte and
Richard Dorrance and
Le Liang and
Lu Lu},
title = {A Vector Processor for Mean Field Bayesian Channel Estimation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1348--1359},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3077408},
doi = {10.1109/TVLSI.2021.3077408},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DasalukunteDLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongBDLL21,
author = {Yangtao Dong and
Chirn Chye Boon and
Xin Ding and
Chenyang Li and
Zhe Liu},
title = {A Bidirectional Nonlinearly Coupled {QVCO} With Passive Phase Interpolation
for Multiphase Signals Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1480--1484},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3077613},
doi = {10.1109/TVLSI.2021.3077613},
timestamp = {Mon, 10 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DongBDLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuWYD21,
author = {Xinyu Du and
Lidan Wang and
Dengwei Yan and
Shukai Duan},
title = {A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2210--2219},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3106312},
doi = {10.1109/TVLSI.2021.3106312},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DuWYD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElamienMBE21,
author = {Mohamed B. Elamien and
Brent J. Maundy and
Leonid Belostotski and
Ahmed S. Elwakil},
title = {Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative
Examples},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1850--1860},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3109560},
doi = {10.1109/TVLSI.2021.3109560},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElamienMBE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElshamySLAS21,
author = {Mohamed Elshamy and
Alhassan Sayed and
Marie{-}Minerve Lou{\"{e}}rat and
Hassan Aboushady and
Haralampos{-}G. Stratigopoulos},
title = {Locking by Untuning: {A} Lock-Less Approach for Analog and Mixed-Signal
{IC} Security},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2130--2142},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3117584},
doi = {10.1109/TVLSI.2021.3117584},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElshamySLAS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EmaraRRAZPB21,
author = {Ahmed S. Emara and
Denis Romanov and
Gordon W. Roberts and
Sadok Aouini and
Soheyl Ziabakhsh and
Mahdi Parvizi and
Naim Ben{-}Hamida},
title = {An Area-Efficient High-Resolution Segmented {\(\Sigma\)}{\(\Delta\)}-DAC
for Built-In Self-Test Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1861--1874},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3106014},
doi = {10.1109/TVLSI.2021.3106014},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EmaraRRAZPB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EnsanG21,
author = {Sina Sayyah Ensan and
Swaroop Ghosh},
title = {ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential
Equation Solver},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {237--241},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3035769},
doi = {10.1109/TVLSI.2020.3035769},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EnsanG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EnsanNKG21,
author = {Sina Sayyah Ensan and
Karthikeyan Nagarajan and
Mohammad Nasim Imtiaz Khan and
Swaroop Ghosh},
title = {{SCARE:} Side Channel Attack on In-Memory Computing for Reverse Engineering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2040--2051},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3110744},
doi = {10.1109/TVLSI.2021.3110744},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EnsanNKG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErozanBT21,
author = {Ahmet Turan Erozan and
Simon Bosse and
Mehdi B. Tahoori},
title = {Defect Detection in Transparent Printed Electronics Using Learning-Based
Optical Inspection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1505--1517},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3082476},
doi = {10.1109/TVLSI.2021.3082476},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ErozanBT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Gao0L0Z21,
author = {Jiajing Gao and
Wei Zhang and
Yanyan Liu and
Hao Wang and
Jianhan Zhao},
title = {High-Performance Concatenation Decoding of Reed-Solomon Codes With
{SPC} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1670--1674},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3097155},
doi = {10.1109/TVLSI.2021.3097155},
timestamp = {Fri, 17 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Gao0L0Z21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaoZCGUR21,
author = {Zhen Gao and
Lingling Zhang and
Yinghao Cheng and
Kangkang Guo and
Anees Ullah and
Pedro Reviriego},
title = {Design of FPGA-Implemented Reed-Solomon Erasure Code {(RS-EC)} Decoders
With Fault Detection and Location on User Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1073--1082},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3066804},
doi = {10.1109/TVLSI.2021.3066804},
timestamp = {Thu, 21 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaoZCGUR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaryfallouSSASE21,
author = {Dimitrios Garyfallou and
Stavros Simoglou and
Nikolaos Sketopoulos and
Charalampos Antoniadis and
Christos P. Sotiriou and
Nestor E. Evmorfopoulos and
George I. Stamoulis},
title = {Gate Delay Estimation With Library Compatible Current Source Models
and Effective Capacitance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {962--972},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3061484},
doi = {10.1109/TVLSI.2021.3061484},
timestamp = {Tue, 01 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaryfallouSSASE21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GarzonGHLT21,
author = {Esteban Garz{\'{o}}n and
Yosi Greenblatt and
Odem Harel and
Marco Lanuzza and
Adam Teman},
title = {Gain-Cell Embedded {DRAM} Under Cryogenic Operation - {A} First Study},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1319--1324},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3081043},
doi = {10.1109/TVLSI.2021.3081043},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GarzonGHLT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GiraldoJV21,
author = {Juan Sebastian Piedrahita Giraldo and
Vikram Jain and
Marian Verhelst},
title = {Efficient Execution of Temporal Convolutional Networks for Embedded
Keyword Spotting},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2220--2228},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3120189},
doi = {10.1109/TVLSI.2021.3120189},
timestamp = {Wed, 02 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GiraldoJV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GundiSBPRC21,
author = {Noel Daniel Gundi and
Tahmoures Shabanian and
Prabal Basu and
Pramesh Pandey and
Sanghamitra Roy and
Koushik Chakraborty},
title = {{EFFORT:} {A} Comprehensive Technique to Tackle Timing Violations
and Improve Energy Efficiency of Near-Threshold Tensor Processing
Units},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1790--1799},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3106858},
doi = {10.1109/TVLSI.2021.3106858},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GundiSBPRC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuoL21,
author = {Wenbo Guo and
Shuguo Li},
title = {Fast Binary Counters and Compressors Generated by Sorting Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1220--1230},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3067010},
doi = {10.1109/TVLSI.2021.3067010},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuoL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HammadWGM21,
author = {Karim Hammad and
Zhongpan Wu and
Ebrahim Ghafar{-}Zadeh and
Sebastian Magierowski},
title = {A Scalable Hardware Accelerator for Mobile {DNA} Sequencing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {273--286},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3044527},
doi = {10.1109/TVLSI.2020.3044527},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HammadWGM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeidarpurM21,
author = {Moslem Heidarpur and
Mitra Mirhassani},
title = {An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field
Multiplier for {FGPA} Implementation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {667--676},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3058509},
doi = {10.1109/TVLSI.2021.3058509},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeidarpurM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeoK21,
author = {Jeongwoo Heo and
Taewhan Kim},
title = {Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline
Controller},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1437--1450},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3073383},
doi = {10.1109/TVLSI.2021.3073383},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeoK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HosseiniMPMCHM21,
author = {Morteza Hosseini and
Nitheesh Kumar Manjunath and
Bharat Prakash and
Arnab Neelim Mazumder and
Vandana Chandrareddy and
Houman Homayoun and
Tinoosh Mohsenin},
title = {Cyclic Sparsely Connected Architectures for Compact Deep Convolutional
Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1757--1770},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3110250},
doi = {10.1109/TVLSI.2021.3110250},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HosseiniMPMCHM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HowladarRR21,
author = {Pampa Howladar and
Pranab Roy and
Hafizur Rahaman},
title = {Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique
for Intelligent Cross-Contamination Avoidance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1451--1464},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3071410},
doi = {10.1109/TVLSI.2021.3071410},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HowladarRR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangC21,
author = {Chi{-}Ray Huang and
Lih{-}Yih Chiou},
title = {An Energy-Efficient Conditional Biasing Write Assist With Built-In
Time-Based Write-Margin-Tracking for Low-Voltage {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1586--1590},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3084041},
doi = {10.1109/TVLSI.2021.3084041},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangCY21,
author = {Wei{-}pei Huang and
Ray C. C. Cheung and
Hong Yan},
title = {An Efficient Parallel Processor for Dense Tensor Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1335--1347},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3080318},
doi = {10.1109/TVLSI.2021.3080318},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangCY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangJPLY21,
author = {Shanshi Huang and
Hongwu Jiang and
Xiaochen Peng and
Wantong Li and
Shimeng Yu},
title = {Secure {XOR-CIM} Engine: Compute-In-Memory {SRAM} Architecture With
Embedded {XOR} Encryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2027--2039},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3120296},
doi = {10.1109/TVLSI.2021.3120296},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangJPLY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HungCLSC21,
author = {Yi{-}Wen Hung and
Yung{-}Chih Chen and
Chi Lo and
Austin Go So and
Shih{-}Chieh Chang},
title = {Dynamic Workload Allocation for Edge Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {519--529},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3049520},
doi = {10.1109/TVLSI.2021.3049520},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HungCLSC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HungLLC21,
author = {Shao{-}Chun Hung and
Yi{-}Chen Lu and
Sung Kyu Lim and
Krishnendu Chakrabarty},
title = {Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic
3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1875--1888},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3108787},
doi = {10.1109/TVLSI.2021.3108787},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HungLLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IsmailiANG21,
author = {Zakaria El Alaoui Ismaili and
Wessam Ajib and
Frederic Nabki and
Fran{\c{c}}ois Gagnon},
title = {A 0.1-9-GHz Frequency Synthesizer for Avionic {SDR} Applications in
0.13-{\(\mu\)}m {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2119--2129},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3123140},
doi = {10.1109/TVLSI.2021.3123140},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IsmailiANG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JaoRSN21,
author = {Nicholas Jao and
Akshay Krishna Ramanathan and
John Sampson and
Vijaykrishnan Narayanan},
title = {Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected
Crossbars},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2186--2196},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3114186},
doi = {10.1109/TVLSI.2021.3114186},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JaoRSN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JavadiNTMC21,
author = {Mohsen Javadi and
Hossein Miar Naimi and
Saheed Tijani and
Danilo Manstretta and
Rinaldo Castello},
title = {A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs
Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1360--1369},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3077084},
doi = {10.1109/TVLSI.2021.3077084},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JavadiNTMC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JevticYCOSK21,
author = {Ruzica Jevtic and
Marko Ylitolva and
Clara Calonge and
Martti Ojanen and
Tero S{\"{a}}ntti and
Lauri Koskinen},
title = {{EM} Side-Channel Countermeasure for Switched-Capacitor {DC-DC} Converters
Based on Amplitude Modulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1061--1072},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3070687},
doi = {10.1109/TVLSI.2021.3070687},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JevticYCOSK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiSP21,
author = {Daehan Ji and
Dongyeob Shin and
Jongsun Park},
title = {An Error Compensation Technique for Low-Voltage {DNN} Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {397--408},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3041517},
doi = {10.1109/TVLSI.2020.3041517},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JiSP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KahngKKX21,
author = {Andrew B. Kahng and
Seokhyeong Kang and
Seungwon Kim and
Bangqi Xu},
title = {Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {591--604},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3041665},
doi = {10.1109/TVLSI.2020.3041665},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KahngKKX21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KamYL21,
author = {Dongyun Kam and
Hoyoung Yoo and
Youngjoo Lee},
title = {Ultralow-Latency Successive Cancellation Polar Decoding Architecture
Using Tree-Level Parallelism},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1083--1094},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3068965},
doi = {10.1109/TVLSI.2021.3068965},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KamYL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Khaddam-Aljameh21,
author = {Riduan Khaddam{-}Aljameh and
Pier Andrea Francese and
Luca Benini and
Evangelos Eleftheriou},
title = {An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision
That Scales Linearly in Area, Time, and Power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {372--385},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3037871},
doi = {10.1109/TVLSI.2020.3037871},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Khaddam-Aljameh21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanCXHB21,
author = {Nadir Khan and
Jorge Castro{-}God{\'{\i}}nez and
Shixiang Xue and
J{\"{o}}rg Henkel and
J{\"{u}}rgen Becker},
title = {Automatic Floorplanning and Standalone Generation of Bitstream-Level
{IP} Cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {38--50},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3023548},
doi = {10.1109/TVLSI.2020.3023548},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanCXHB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanS21,
author = {Fatima Hameed Khan and
Wala Saadeh},
title = {An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {950--961},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3058047},
doi = {10.1109/TVLSI.2021.3058047},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimNKCP21,
author = {Suchang Kim and
Seungho Na and
Byeong Yong Kong and
Jaewoong Choi and
In{-}Cheol Park},
title = {Real-Time SSDLite Object Detection on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1192--1205},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3064639},
doi = {10.1109/TVLSI.2021.3064639},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimNKCP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimPK21,
author = {Taehwan Kim and
Heechun Park and
Taewhan Kim},
title = {Allocation of Always-On State Retention Storage for Power Gated Circuits
- Steady-State- Driven Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {499--511},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3047056},
doi = {10.1109/TVLSI.2020.3047056},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimPK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KongL21,
author = {Tianqi Kong and
Shuguo Li},
title = {Design and Analysis of Approximate 4-2 Compressors for High-Accuracy
Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1771--1781},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3104145},
doi = {10.1109/TVLSI.2021.3104145},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KongL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarCEMLTKTDK21,
author = {Saurabh Kumar and
Minki Cho and
Luke R. Everson and
Andres Malavasi and
Dan Lake and
Carlos Tokunaga and
Muhammad M. Khellah and
James W. Tschanz and
Vivek De and
Chris H. Kim},
title = {A Back-Sampling Chain Technique for Accelerated Detection, Characterization,
and Reconstruction of Radiation-Induced Transient Pulses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2086--2097},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3119462},
doi = {10.1109/TVLSI.2021.3119462},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarCEMLTKTDK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarM21,
author = {Sandeep Kumar and
Atin Mukherjee},
title = {A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing
Latch for Radiation-Prone Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2076--2085},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3110135},
doi = {10.1109/TVLSI.2021.3110135},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KunduBRNB21,
author = {Shamik Kundu and
Suvadeep Banerjee and
Arnab Raha and
Suriyaprakash Natarajan and
Kanad Basu},
title = {Toward Functional Safety of Systolic Array-Based Deep Learning Hardware
Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {485--498},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3048829},
doi = {10.1109/TVLSI.2020.3048829},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KunduBRNB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LarssonXM21,
author = {Erik Larsson and
Zehang Xiang and
Prathamesh Murali},
title = {Graceful Degradation of Reconfigurable Scan Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1475--1479},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3076593},
doi = {10.1109/TVLSI.2021.3076593},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LarssonXM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeCLL21,
author = {Yu{-}Hsuan Lee and
Tzu{-}Chieh Chen and
Hsuan{-}Chi Liang and
Jian{-}Xiang Liao},
title = {Algorithm and Architecture Design of {FAST-C} Image Corner Detection
Engine},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {788--799},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3031294},
doi = {10.1109/TVLSI.2020.3031294},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeCLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeJKNNNHCK21,
author = {Sanghun Lee and
Kisang Jung and
Hak Seong Kim and
Huan Nguyen and
Thinh Nguyen and
Luan Nguyen and
Cuong Huynh and
Kunhee Cho and
Jusung Kim},
title = {Frequency-Locked {RF} Power Oscillator With 43-dBm Output Power and
58{\%} Efficiency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {739--746},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056720},
doi = {10.1109/TVLSI.2021.3056720},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeJKNNNHCK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLJ21,
author = {Gwangho Lee and
Sunwoo Lee and
Dongsuk Jeon},
title = {Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network
Training},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1680--1684},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3097341},
doi = {10.1109/TVLSI.2021.3097341},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeePJ21,
author = {Kwang Woo Lee and
Hyun Kook Park and
Seong{-}Ook Jung},
title = {Adaptive Sensing Voltage Modulation Technique in Cross-Point {OTS-PRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {631--642},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3058150},
doi = {10.1109/TVLSI.2021.3058150},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeePJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCPJ21,
author = {Jun Li and
Paul Chow and
Yuanxi Peng and
Tian Jiang},
title = {{FPGA} Implementation of an Improved {OMP} for Compressive Sensing
Reconstruction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {259--272},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3030906},
doi = {10.1109/TVLSI.2020.3030906},
timestamp = {Mon, 13 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCPJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWMSCZ21,
author = {Gang Li and
Pengjun Wang and
Xuejiao Ma and
Yijian Shi and
Bo Chen and
Yuejun Zhang},
title = {A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening
and Power-Gating Strategies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {100--111},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3030945},
doi = {10.1109/TVLSI.2020.3030945},
timestamp = {Tue, 06 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWMSCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangLCCHSJMH21,
author = {Zhuojun Liang and
Dongxu Lv and
Chao Cui and
Hai{-}Bao Chen and
Weifeng He and
Weiguang Sheng and
Naifeng Jing and
Zhigang Mao and
Guanghui He},
title = {A 3.85-Gb/s 8 {\texttimes} 8 Soft-Output {MIMO} Detector With Lattice-Reduction-Aided
Channel Preprocessing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {307--320},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3036822},
doi = {10.1109/TVLSI.2020.3036822},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangLCCHSJMH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCHSCL21,
author = {Jai{-}Ming Lin and
Tai{-}Ting Chen and
Hao{-}Yuan Hsieh and
Ya{-}Ting Shyu and
Yeong{-}Jar Chang and
Juin{-}Ming Lu},
title = {Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models
With Thermal-Force Modulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {985--997},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3062669},
doi = {10.1109/TVLSI.2021.3062669},
timestamp = {Tue, 01 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCHSCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCHSCL21a,
author = {Jai{-}Ming Lin and
Wei{-}Yi Chang and
Hao{-}Yuan Hsieh and
Ya{-}Ting Shyu and
Yeong{-}Jar Chang and
Juin{-}Ming Lu},
title = {Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules
in a Fixed-Outline 3-D {IC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1652--1664},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3100343},
doi = {10.1109/TVLSI.2021.3100343},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCHSCL21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinDYCL21,
author = {Jai{-}Ming Lin and
You{-}Lun Deng and
Ya{-}Chu Yang and
Jia{-}Jian Chen and
Po{-}Chen Lu},
title = {Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm
for Mixed-Size Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {973--984},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3057921},
doi = {10.1109/TVLSI.2021.3057921},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinDYCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LingLTSSY21,
author = {Ming Ling and
Qingde Lin and
Ke Tan and
Tianxiang Shao and
Shan Shen and
Jun Yang},
title = {A Design of Timing Speculation SRAM-Based {L1} Caches With {PVT} Autotracking
Under Near-Threshold Voltages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2197--2209},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3120653},
doi = {10.1109/TVLSI.2021.3120653},
timestamp = {Tue, 15 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LingLTSSY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuLDZ21,
author = {Jian Liu and
Shubin Liu and
Ruixue Ding and
Zhangming Zhu},
title = {A Conversion Mode Reconfigurable {SAR} {ADC} for Multistandard Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {895--903},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3059857},
doi = {10.1109/TVLSI.2021.3059857},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuLDZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuMMMRTW21,
author = {Yingdi Liu and
Sylwester Milewski and
Grzegorz Mrugalski and
Nilanjan Mukherjee and
Janusz Rajski and
Jerzy Tyszer and
Bartosz Wlodarczak},
title = {X-Tolerant Compactor maXpress for In-System Test Applications With
Observation Scan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1553--1566},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3092421},
doi = {10.1109/TVLSI.2021.3092421},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuMMMRTW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuTRHZP21,
author = {Zhifei Lu and
He Tang and
Zhaofeng Ren and
Ruogu Hua and
Haoyu Zhuang and
Xizhu Peng},
title = {A Timing Mismatch Background Calibration Algorithm With Improved Accuracy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1591--1595},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3082719},
doi = {10.1109/TVLSI.2021.3082719},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuTRHZP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuWWZYYHL21,
author = {Yingchun Lu and
Xinyu Wang and
Yanjie Wang and
Yuan Zhang and
Liang Yao and
Maoxiang Yi and
Zhengfeng Huang and
Huaguo Liang},
title = {Pure Digital Scalable Mixed Entropy Separation Structure for Physical
Unclonable Function and True Random Number Generator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1922--1929},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3116104},
doi = {10.1109/TVLSI.2021.3116104},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuWWZYYHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LyuMZWL21,
author = {Fei Lyu and
Zhelong Mao and
Jin Zhang and
Yu Wang and
Yuanyong Luo},
title = {PWL-Based Architecture for the Logarithmic Computation of Floating-Point
Numbers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1470--1474},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3081572},
doi = {10.1109/TVLSI.2021.3081572},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LyuMZWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MachSZB21,
author = {Stefan Mach and
Fabian Schuiki and
Florian Zaruba and
Luca Benini},
title = {FPnew: An Open-Source Multiformat Floating-Point Unit Architecture
for Energy-Proportional Transprecision Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {774--787},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3044752},
doi = {10.1109/TVLSI.2020.3044752},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MachSZB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahdiKP21,
author = {Ahmed Mahdi and
Nikos Kanistras and
Vassilis Paliouras},
title = {A Multirate Fully Parallel {LDPC} Encoder for the {IEEE} 802.11n/ac/ax
{QC-LDPC} Codes Based on Reduced Complexity {XOR} Trees},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {51--64},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3034046},
doi = {10.1109/TVLSI.2020.3034046},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MahdiKP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MahmoudiTD21,
author = {Azad Mahmoudi and
Pooya Torkzadeh and
Massoud Dousti},
title = {A 6-Bit 1.5-GS/s {SAR} {ADC} With Smart Speculative Two-Tap Embedded
{DFE} in 130-nm {CMOS} for Wireline Receiver Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {871--882},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056316},
doi = {10.1109/TVLSI.2021.3056316},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MahmoudiTD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MansourMAAAPA21,
author = {Islam Mansour and
Marwa Mansour and
Mohamed Aboualalaa and
Ahmed Allam and
Adel B. Abdel{-}Rahman and
Ramesh K. Pokharel and
Mohammed Abo{-}Zahhad},
title = {A Multiband {VCO} Using a Switched Series Resonance for Fine Frequency
Tuning Sensitivity and Phase Noise Improvement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2163--2171},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3115050},
doi = {10.1109/TVLSI.2021.3115050},
timestamp = {Fri, 17 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MansourMAAAPA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarchisioMH021,
author = {Alberto Marchisio and
Vojtech Mrazek and
Muhammad Abdullah Hanif and
Muhammad Shafique},
title = {{FEECA:} Design Space Exploration for Low-Latency and Energy-Efficient
Capsule Network Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {716--729},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3059518},
doi = {10.1109/TVLSI.2021.3059518},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MarchisioMH021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MasadehHT21,
author = {Mahmoud Masadeh and
Osman Hasan and
Sofi{\`{e}}ne Tahar},
title = {Machine-Learning-Based Self-Tunable Design of Approximate Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {800--813},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056243},
doi = {10.1109/TVLSI.2021.3056243},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MasadehHT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MedeirosFWTPH21,
author = {Guilherme Cardoso Medeiros and
Moritz Fieback and
Lizhou Wu and
Mottaqiallah Taouil and
Let{\'{\i}}cia Maria Bolzani Poehls and
Said Hamdioui},
title = {Hard-to-Detect Fault Analysis in FinFET SRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1271--1284},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3071940},
doi = {10.1109/TVLSI.2021.3071940},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MedeirosFWTPH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MiketicS21,
author = {Ivan Miketic and
Emre Salman},
title = {PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse
Engineering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1285--1296},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3078567},
doi = {10.1109/TVLSI.2021.3078567},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MiketicS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MishtyS21,
author = {Kaniz Mishty and
Mehdi Sadi},
title = {Designing Efficient and High-Performance {AI} Accelerators With Customized
{STT-MRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1730--1742},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3105958},
doi = {10.1109/TVLSI.2021.3105958},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MishtyS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MokLK21,
author = {Jungil Mok and
Hyeonchan Lim and
Sungho Kang},
title = {Enhanced Postbond Test Architecture for Bridge Defects Between the
TSVs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1164--1177},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3063651},
doi = {10.1109/TVLSI.2021.3063651},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MokLK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MukherjeeTSLMMM21,
author = {Nilanjan Mukherjee and
Daniel Tille and
Mahendar Sapati and
Yingdi Liu and
Jeffrey Mayer and
Sylwester Milewski and
Elham K. Moghaddam and
Janusz Rajski and
Jedrzej Solecki and
Jerzy Tyszer},
title = {Time and Area Optimized Testing of Automotive ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {76--88},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3025138},
doi = {10.1109/TVLSI.2020.3025138},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MukherjeeTSLMMM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MukimB21,
author = {Prashansa Mukim and
Forrest Brewer},
title = {Multiwire Phase Encoding: {A} Signaling Strategy for High-Bandwidth,
Low-Power Data Movement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1543--1552},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3087585},
doi = {10.1109/TVLSI.2021.3087585},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MukimB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuraliP0TDSKL21,
author = {Gauthaman Murali and
Heechun Park and
Eric Qin and
Hakki Mert Torun and
Majid Ahadi Dolatsara and
Madhavan Swaminathan and
Tushar Krishna and
Sung Kyu Lim},
title = {Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D
Heterogeneous Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {605--616},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3058300},
doi = {10.1109/TVLSI.2021.3058300},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MuraliP0TDSKL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MuraliSYL21,
author = {Gauthaman Murali and
Xiaoyu Sun and
Shimeng Yu and
Sung Kyu Lim},
title = {Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using
Resistive {RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {386--396},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3042411},
doi = {10.1109/TVLSI.2020.3042411},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MuraliSYL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Murmann21,
author = {Boris Murmann},
title = {Mixed-Signal Computing for Deep Neural Network Inference},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {3--13},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3020286},
doi = {10.1109/TVLSI.2020.3020286},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Murmann21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NadalB21,
author = {J{\'{e}}r{\'{e}}my Nadal and
Amer Baghdadi},
title = {Parallel and Flexible 5G {LDPC} Decoder Architecture Targeting {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1141--1151},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3072866},
doi = {10.1109/TVLSI.2021.3072866},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NadalB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NagarajanAKDCG21,
author = {Karthikeyan Nagarajan and
Farid Uddin Ahmed and
Mohammad Nasim Imtiaz Khan and
Asmit De and
Masud H. Chowdhury and
Swaroop Ghosh},
title = {SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for
Highly Secure Emerging {NVM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1518--1528},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3087734},
doi = {10.1109/TVLSI.2021.3087734},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NagarajanAKDCG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NiWLW21,
author = {Meng Ni and
Xiao Wang and
Fule Li and
Zhihua Wang},
title = {A 13-bit 312.5-MS/s Pipelined {SAR} {ADC} With Open-Loop Integrator-Based
Residue Amplifier and Gain-Stabilized Integration Time Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1416--1427},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3078689},
doi = {10.1109/TVLSI.2021.3078689},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NiWLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NiasarAK21,
author = {Mojtaba Bisheh{-}Niasar and
Reza Azarderakhsh and
Mehran Mozaffari Kermani},
title = {Cryptographic Accelerators for Digital Signature Based on Ed25519},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1297--1305},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3077885},
doi = {10.1109/TVLSI.2021.3077885},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NiasarAK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NighO21,
author = {Chris Nigh and
Alex Orailoglu},
title = {AdaTrust: Combinational Hardware Trojan Detection Through Adaptive
Test Pattern Construction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {544--557},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3053553},
doi = {10.1109/TVLSI.2021.3053553},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NighO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NiuFYWLLW21,
author = {Na Niu and
Fangfa Fu and
Bing Yang and
Qiang Wang and
Xinpeng Li and
Fengchang Lai and
Jinxiang Wang},
title = {{PFHA:} {A} Novel Page Migration Algorithm for Hybrid Memory Embedded
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1685--1692},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3090476},
doi = {10.1109/TVLSI.2021.3090476},
timestamp = {Thu, 29 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NiuFYWLLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OkuharaEDPBBR21,
author = {Hayate Okuhara and
Ahmed Elnaqib and
Martino Dazzi and
Pierpaolo Palestri and
Simone Benatti and
Luca Benini and
Davide Rossi},
title = {A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data
Link for Ultralow-Power IoT End-Nodes in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1800--1811},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3108806},
doi = {10.1109/TVLSI.2021.3108806},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OkuharaEDPBBR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PalestriEMSBBRN21,
author = {Pierpaolo Palestri and
Ahmed Elnaqib and
Davide Menin and
Klaid Shyti and
Francesco Brandonisio and
Andrea Bandiziol and
Davide Rossi and
Roberto Nonis},
title = {Analytical Modeling of Jitter in Bang-Bang {CDR} Circuits Featuring
Phase Interpolation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1392--1401},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3068450},
doi = {10.1109/TVLSI.2021.3068450},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PalestriEMSBBRN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkJKNY21,
author = {Seongsik Park and
Jaehee Jang and
Sei Joon Kim and
Byunggook Na and
Sungroh Yoon},
title = {Memory-Augmented Neural Networks on {FPGA} for Real-Time and Energy-Efficient
Question Answering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {162--175},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3037166},
doi = {10.1109/TVLSI.2020.3037166},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkJKNY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaulinA0B21,
author = {Gianna Paulin and
Renzo Andri and
Francesco Conti and
Luca Benini},
title = {RNN-Based Radio Resource Management on Multicore {RISC-V} Accelerator
Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1624--1637},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3093242},
doi = {10.1109/TVLSI.2021.3093242},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PaulinA0B21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PereiraPCCAB21,
author = {Pedro Tau{\~{a}} Lopes Pereira and
Guilherme Paim and
Patr{\'{\i}}cia {\"{U}}cker Leleu da Costa and
Eduardo Ant{\^{o}}nio C{\'{e}}sar da Costa and
S{\'{e}}rgio Jose Melo de Almeida and
Sergio Bampi},
title = {Architectural Exploration for Energy-Efficient Fixed-Point Kalman
Filter {VLSI} Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1402--1415},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3075379},
doi = {10.1109/TVLSI.2021.3075379},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PereiraPCCAB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PilatoCSGK21,
author = {Christian Pilato and
Animesh Basak Chowdhury and
Donatella Sciuto and
Siddharth Garg and
Ramesh Karri},
title = {{ASSURE:} {RTL} Locking Against an Untrusted Foundry},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1306--1318},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3074004},
doi = {10.1109/TVLSI.2021.3074004},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PilatoCSGK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz21,
author = {Irith Pomeranz},
title = {Partitioning Functional Test Sequences Into Multicycle Functional
Broadside Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {89--99},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3029729},
doi = {10.1109/TVLSI.2020.3029729},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz21a,
author = {Irith Pomeranz},
title = {Test Compaction by Backward and Forward Extension of Multicycle Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {242--246},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3028005},
doi = {10.1109/TVLSI.2020.3028005},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz21b,
author = {Irith Pomeranz},
title = {Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive
Faults for Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1500--1504},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3081046},
doi = {10.1109/TVLSI.2021.3081046},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz21b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzL21,
author = {Irith Pomeranz and
Xijiang Lin},
title = {Single Test Type to Replace Broadside and Skewed-Load Tests for Transition
Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {423--433},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3038368},
doi = {10.1109/TVLSI.2020.3038368},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PutraH021,
author = {Rachmad Vidya Wicaksana Putra and
Muhammad Abdullah Hanif and
Muhammad Shafique},
title = {ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management
and Data Organization for Deep Neural Network Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {702--715},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3060509},
doi = {10.1109/TVLSI.2021.3060509},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PutraH021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QuZEWL21,
author = {Chenbing Qu and
Zhangming Zhu and
Yunfei En and
Liwei Wang and
Xiaoxian Liu},
title = {Area-Efficient Extended 3-D Inductor Based on {TSV} Technology for
{RF} Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {287--296},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3036385},
doi = {10.1109/TVLSI.2020.3036385},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/QuZEWL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RamanathanCW21,
author = {Nadesh Ramanathan and
George A. Constantinides and
John Wickerson},
title = {Global Analysis of {C} Concurrency in High-Level Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {24--37},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3026112},
doi = {10.1109/TVLSI.2020.3026112},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RamanathanCW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaoS21,
author = {Vaibhav Venugopal Rao and
Ioannis Savidis},
title = {Performance and Security Analysis of Parameter-Obfuscated Analog Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2013--2026},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3109062},
doi = {10.1109/TVLSI.2021.3109062},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RaoS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RashidFTHBR21,
author = {M. Imtiaz Rashid and
Farah Ferdaus and
Bashir M. Sabquat Bahar Talukder and
Paul Henny and
Aubrey N. Beal and
Md. Tauhidur Rahman},
title = {True Random Number Generation Using Latency Variations of {FRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {14--23},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3018998},
doi = {10.1109/TVLSI.2020.3018998},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RashidFTHBR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Realpe-MunozVA21,
author = {Paulo Realpe{-}Mu{\~{n}}oz and
Jaime Velasco{-}Medina and
Guillermo Adolfo{-}David},
title = {Design of an {S-ECIES} Cryptoprocessor Using Gaussian Normal Bases
Over GF(2\({}^{\mbox{m}}\))},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {657--666},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3057985},
doi = {10.1109/TVLSI.2021.3057985},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Realpe-MunozVA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReubenP21,
author = {John Reuben and
Stefan Pechmann},
title = {Accelerated Addition in Resistive {RAM} Array Using Parallel-Friendly
Majority Gates},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1108--1121},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3068470},
doi = {10.1109/TVLSI.2021.3068470},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ReubenP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoySJR21,
author = {Sourjya Roy and
Shrihari Sridharan and
Shubham Jain and
Anand Raghunathan},
title = {TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar
Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {730--738},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3063543},
doi = {10.1109/TVLSI.2021.3063543},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RoySJR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchiavoneRMGSWY21,
author = {Pasquale Davide Schiavone and
Davide Rossi and
Alfio Di Mauro and
Frank K. G{\"{u}}rkaynak and
Timothy Saxe and
Mao Wang and
Ket Chong Yap and
Luca Benini},
title = {Arnold: An eFPGA-Augmented {RISC-V} SoC for Flexible and Low-Power
IoT End Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {677--690},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3058162},
doi = {10.1109/TVLSI.2021.3058162},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SchiavoneRMGSWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SeckinerK21,
author = {Soner Se{\c{c}}kiner and
Sel{\c{c}}uk K{\"{o}}se},
title = {Preprocessing of the Physical Leakage Information to Combine Side-Channel
Distinguishers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2052--2063},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3115420},
doi = {10.1109/TVLSI.2021.3115420},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SeckinerK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SenguptaR21,
author = {Anirban Sengupta and
Mahendra Rathor},
title = {Facial Biometric for Securing Hardware Accelerators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {112--123},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3029245},
doi = {10.1109/TVLSI.2020.3029245},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SenguptaR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShahabuddinHJS21,
author = {Shahriar Shahabuddin and
Ilkka Hautala and
Markku J. Juntti and
Christoph Studer},
title = {ADMM-Based Infinity-Norm Detection for Massive {MIMO:} Algorithm and
{VLSI} Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {4},
pages = {747--759},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056946},
doi = {10.1109/TVLSI.2021.3056946},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShahabuddinHJS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShahbaziK21,
author = {Karim Shahbazi and
Seok{-}Bum Ko},
title = {Area-Efficient Nano-AES Implementation for Internet-of-Things Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {136--148},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3033928},
doi = {10.1109/TVLSI.2020.3033928},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShahbaziK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Shrestha21,
author = {Rahul Shrestha},
title = {A Multiple-Radix MAP-Decoder Microarchitecture and Its {ASIC} Implementation
for Energy-Efficient and Variable-Throughput Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {65--75},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3031001},
doi = {10.1109/TVLSI.2020.3031001},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Shrestha21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SiddiquiLK21,
author = {M. Sultan M. Siddiqui and
Zhao Chuan Lee and
Tony Tae{-}Hyoung Kim},
title = {A 16-kb 9T Ultralow-Voltage {SRAM} With Column-Based Split Cell-VSS,
Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm
{FDSOI}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1707--1719},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3102675},
doi = {10.1109/TVLSI.2021.3102675},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SiddiquiLK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghBJHCG21,
author = {Kamlesh Singh and
Barry de Bruin and
Hailong Jiao and
Jos Huisken and
Henk Corporaal and
Jos{\'{e}} Pineda de Gyvez},
title = {Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold
Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1039--1051},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3071464},
doi = {10.1109/TVLSI.2021.3071464},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghBJHCG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SinghCRTK21,
author = {Gyanendra Singh and
Samba Raju Chiluveru and
Balasubramanian Raman and
Manoj Tripathy and
Brajesh Kumar Kaushik},
title = {Novel Architecture for Lifting Discrete Wavelet Packet Transform With
Arbitrary Tree Structure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1490--1494},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3079989},
doi = {10.1109/TVLSI.2021.3079989},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SinghCRTK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongHJL21,
author = {Yongwoon Song and
Jooyoung Hwang and
Insoon Jo and
Hyukjun Lee},
title = {Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {2008--2012},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3116272},
doi = {10.1109/TVLSI.2021.3116272},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SongHJL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SongHK21,
author = {Junyoung Song and
Sewook Hwang and
Chulwoo Kim},
title = {A 32-Gb/s Dual-Mode Transceiver With One-Tap {FIR} and Two-Tap {IIR}
{RX} Only Equalization in 65-nm {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1567--1574},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3086325},
doi = {10.1109/TVLSI.2021.3086325},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SongHK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunLH21,
author = {Yin Sun and
Jongjoo Lee and
Chulsoon Hwang},
title = {A Generalized Power Supply Induced Jitter Model Based on Power Supply
Rejection Ratio Response},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1052--1060},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3072799},
doi = {10.1109/TVLSI.2021.3072799},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunLH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunnyMTNP21,
author = {Febin P. Sunny and
Asif Mirza and
Ishan G. Thakkar and
Mahdi Nikdast and
Sudeep Pasricha},
title = {{ARXON:} {A} Framework for Approximate Communication Over Photonic
Networks-on-Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1206--1219},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3066990},
doi = {10.1109/TVLSI.2021.3066990},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SunnyMTNP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Taherinejad21,
author = {Nima Taherinejad},
title = {{SIXOR:} Single-Cycle In-Memristor {XOR}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {925--935},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3062293},
doi = {10.1109/TVLSI.2021.3062293},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Taherinejad21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TemenosS21,
author = {Nikos Temenos and
Paul P. Sotiriadis},
title = {Nonscaling Adders and Subtracters for Stochastic Computing Using Markov
Chains},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1612--1623},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3095353},
doi = {10.1109/TVLSI.2021.3095353},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TemenosS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TemenosS21a,
author = {Nikos Temenos and
Paul P. Sotiriadis},
title = {Stochastic Computing Max {\&} Min Architectures Using Markov Chains:
Design, Analysis, and Implementation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1813--1823},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3114424},
doi = {10.1109/TVLSI.2021.3114424},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TemenosS21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThakurC21,
author = {Atul Thakur and
Shouri Chatterjee},
title = {A 4.4-mA ESD-Safe 900-MHz {LNA} With 0.9-dB Noise Figure},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {297--306},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3038766},
doi = {10.1109/TVLSI.2020.3038766},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThakurC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThirumoorthiJMK21,
author = {Madhan Thirumoorthi and
Marko Jovanovic and
Mitra Mirhassani and
Mohammed A. S. Khalid},
title = {Design and Evaluation of a Hybrid Chaotic-Bistable Ring {PUF}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1912--1921},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3111588},
doi = {10.1109/TVLSI.2021.3111588},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThirumoorthiJMK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TianLW21,
author = {Jing Tian and
Jun Lin and
Zhongfeng Wang},
title = {Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum
Cryptography},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {359--371},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3041786},
doi = {10.1109/TVLSI.2020.3041786},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/TianLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TsaiCTC21,
author = {Chih{-}Wei Tsai and
Yu{-}Ting Chiu and
Yo{-}Hao Tu and
Kuo{-}Hsing Cheng},
title = {A Wide-Range All-Digital Delay-Locked Loop for {DDR1-DDR5} Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1720--1729},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3098171},
doi = {10.1109/TVLSI.2021.3098171},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TsaiCTC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/UnnikrishnanJSS21,
author = {Vishnu Unnikrishnan and
Okko J{\"{a}}rvinen and
Waqas Siddiqui and
Kari Stadius and
Marko Kosunen and
Jussi Ryyn{\"{a}}nen},
title = {Data Conversion With Subgate-Delay Time Resolution Using Cyclic-Coupled
Ring Oscillators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {203--214},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3031028},
doi = {10.1109/TVLSI.2020.3031028},
timestamp = {Fri, 18 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/UnnikrishnanJSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VangalPHAKKKTDK21,
author = {Sriram R. Vangal and
Somnath Paul and
Steven Hsu and
Amit Agarwal and
Saurabh Kumar and
Ram Krishnamurthy and
Harish Krishnamurthy and
James W. Tschanz and
Vivek De and
Chris H. Kim},
title = {Wide-Range Many-Core SoC Design in Scaled {CMOS:} Challenges and Opportunities},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {843--856},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3061649},
doi = {10.1109/TVLSI.2021.3061649},
timestamp = {Thu, 24 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VangalPHAKKKTDK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VazGVA21,
author = {Pablo Ilha Vaz and
Patrick Girard and
Arnaud Virazel and
Hassen Aziza},
title = {Improving {TID} Radiation Robustness of a {CMOS} OxRAM-Based Neuron
Circuit by Using Enclosed Layout Transistors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1122--1131},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3067446},
doi = {10.1109/TVLSI.2021.3067446},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/VazGVA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangCBCP21,
author = {Juncheng Wang and
Xuefeng Chen and
Rui Bai and
Patrick Yin Chiang and
Quan Pan},
title = {A 4 {\texttimes} 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse
and Crosstalk-Remove},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2110--2118},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3120424},
doi = {10.1109/TVLSI.2021.3120424},
timestamp = {Wed, 08 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangCBCP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLCCCWS21,
author = {I{-}Ju Wang and
Yu{-}Pei Liang and
Tseng{-}Yi Chen and
Yuan{-}Hao Chang and
Bo{-}Jun Chen and
Hsin{-}Wen Wei and
Wei{-}Kuan Shih},
title = {Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range
Query Over {NVRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1244--1256},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3072233},
doi = {10.1109/TVLSI.2021.3072233},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLCCCWS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLHLH21,
author = {Qianqian Wang and
Fei Liu and
Cece Huang and
Qianhui Li and
Zongliang Huo},
title = {A Small Ripple and High-Efficiency Wordline Voltage Generator for
3-D nand Flash Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1903--1911},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3113980},
doi = {10.1109/TVLSI.2021.3113980},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLHLH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangTHY21,
author = {Chua{-}Chin Wang and
Lean Karlo S. Tolentino and
Chia{-}Yi Huang and
Chia{-}Hung Yeh},
title = {A 40-nm {CMOS} Multifunctional Computing-in-Memory {(CIM)} Using Single-Ended
Disturb-Free 7T 1-Kb {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2172--2185},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3115970},
doi = {10.1109/TVLSI.2021.3115970},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangTHY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangYZHJM21,
author = {Kai Wang and
Fengkai Yuan and
Lutan Zhao and
Rui Hou and
Zhenzhou Ji and
Dan Meng},
title = {Mitigating Cross-Core Cache Attacks via Suspicious Traffic Detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {347--358},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3041451},
doi = {10.1109/TVLSI.2020.3041451},
timestamp = {Mon, 21 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WangYZHJM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WeiM21,
author = {Po{-}Hsuan Wei and
Boris Murmann},
title = {Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route
Tools},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1838--1849},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3105028},
doi = {10.1109/TVLSI.2021.3105028},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WeiM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuFCW21,
author = {Di Wu and
Xitian Fan and
Wei Cao and
Lingli Wang},
title = {{SWM:} {A} High-Performance Sparse-Winograd Matrix Multiplication
{CNN} Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {936--949},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3060041},
doi = {10.1109/TVLSI.2021.3060041},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WuFCW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuL0LMM21,
author = {Jiangchao Wu and
Hou{-}Man Leong and
Yang Jiang and
Man{-}Kay Law and
Pui{-}In Mak and
Rui Paulo Martins},
title = {A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency
Modulation in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {9},
pages = {1665--1669},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3092066},
doi = {10.1109/TVLSI.2021.3092066},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/WuL0LMM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuHLWCLLC21,
author = {Dawen Xu and
Meng He and
Cheng Liu and
Ying Wang and
Long Cheng and
Huawei Li and
Xiaowei Li and
Kwang{-}Ting Cheng},
title = {{R2F:} {A} Remote Retraining Framework for AIoT Processors With Computing
Errors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1955--1966},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3089224},
doi = {10.1109/TVLSI.2021.3089224},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuHLWCLLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuOLI21,
author = {Zule Xu and
Naoki Ojima and
Shuowei Li and
Tetsuya Iizuka},
title = {An All-Standard-Cell-Based Synthesizable {SAR} {ADC} With Nonlinearity-Compensated
{RDAC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2153--2162},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3122027},
doi = {10.1109/TVLSI.2021.3122027},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuOLI21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuZLWZZLLC21,
author = {Dawen Xu and
Ziyang Zhu and
Cheng Liu and
Ying Wang and
Shuang Zhao and
Lei Zhang and
Huaguo Liang and
Huawei Li and
Kwang{-}Ting Cheng},
title = {Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration
System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {472--484},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3046075},
doi = {10.1109/TVLSI.2020.3046075},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuZLWZZLLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Yan21,
author = {Jin{-}Tai Yan},
title = {Via-Minimization-Oriented Region Routing Under Length-Matching Constraints
in Rapid Single-Flux-Quantum Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1257--1270},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3059786},
doi = {10.1109/TVLSI.2021.3059786},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Yan21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Yan21a,
author = {Jin{-}Tai Yan},
title = {Via-Avoidance-Oriented Interposer Routing for Layer Minimization in
2.5-D {IC} Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1889--1902},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3113918},
doi = {10.1109/TVLSI.2021.3113918},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Yan21a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanSL21,
author = {Chenggang Yan and
Jie Sun and
Weiqiang Liu},
title = {An Efficient High {SFDR} {PDDS} Using High-Pass-Shaped Phase Dithering},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {2003--2007},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3114680},
doi = {10.1109/TVLSI.2021.3114680},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YanSL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanWO21,
author = {Mengting Yan and
Haoran Wei and
Marvin Onabajo},
title = {On-Chip Thermal Profiling to Detect Malicious Activity: System-Level
Concepts and Design of Key Building Blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {530--543},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3047020},
doi = {10.1109/TVLSI.2020.3047020},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanWO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangC21,
author = {Isaak Yang and
Kwang{-}Hyun Cho},
title = {A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {512--518},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3046099},
doi = {10.1109/TVLSI.2020.3046099},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangLC21,
author = {Ching{-}Yuan Yang and
Miao{-}Shan Li and
Ai{-}Jia Chuang},
title = {A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for
Core-to-Core Links},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {883--894},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056506},
doi = {10.1109/TVLSI.2021.3056506},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YangLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangMFS21,
author = {Tiancheng Yang and
Ankit Mittal and
Yunsi Fei and
Aatmesh Shrivastava},
title = {Large Delay Analog Trojans: {A} Silent Fabrication-Time Attack Exploiting
Analog Modalities},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {124--135},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3034878},
doi = {10.1109/TVLSI.2020.3034878},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangMFS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangOLQTZV21,
author = {Chuanshi Yang and
Erik Olieman and
Alphons Litjes and
Lei Qiu and
Kai Tang and
Yuanjin Zheng and
Robert H. M. van Veldhoven},
title = {An Area-Efficient {SAR} {ADC} With Mismatch Error Shaping Technique
Achieving 102-dB {SFDR} 90.2-dB {SNDR} Over 20-kHz Bandwidth},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {8},
pages = {1575--1585},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3087660},
doi = {10.1109/TVLSI.2021.3087660},
timestamp = {Tue, 11 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangOLQTZV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YantirES21,
author = {Hasan Erdem Yantir and
Ahmed M. Eltawil and
Khaled N. Salama},
title = {{IMCA:} An Efficient In-Memory Convolution Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {447--460},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3047641},
doi = {10.1109/TVLSI.2020.3047641},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YantirES21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YarmandKAEP21,
author = {Roohollah Yarmand and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Pooria Esmaeli and
Massoud Pedram},
title = {{OPTIMA:} An Approach for Online Management of Cache Approximation
Levels in Approximate Processing Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {434--446},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3043953},
doi = {10.1109/TVLSI.2020.3043953},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YarmandKAEP21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YokoyamaINK21,
author = {Yoshisato Yokoyama and
Yuichiro Ishii and
Koji Nii and
Kazutoshi Kobayashi},
title = {Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power
MCUs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1495--1499},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3082760},
doi = {10.1109/TVLSI.2021.3082760},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YokoyamaINK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Yoshimura21,
author = {Tsutomu Yoshimura},
title = {Study of Injection Pulling of Oscillators in Phase-Locked Loops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {321--332},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3037895},
doi = {10.1109/TVLSI.2020.3037895},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Yoshimura21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Yoshioka21,
author = {Kentaro Yoshioka},
title = {VCO-Based Comparator: {A} Fully Adaptive Noise Scaling Comparator
for High-Precision and Low-Power {SAR} ADCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {12},
pages = {2143--2152},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3119691},
doi = {10.1109/TVLSI.2021.3119691},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Yoshioka21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YouYYQ21,
author = {Heng You and
Jia Yuan and
Zenghui Yu and
Shushan Qiao},
title = {Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free
Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {1022--1032},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3061921},
doi = {10.1109/TVLSI.2021.3061921},
timestamp = {Sun, 16 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YouYYQ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangNLYWZ21,
author = {Qihui Zhang and
Ning Ning and
Jing Li and
Qi Yu and
Kejun Wu and
Zhong Zhang},
title = {A Second-Order Noise-Shaping {SAR} {ADC} Using Two Passive Integrators
Separated by the Comparator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {227--231},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3033415},
doi = {10.1109/TVLSI.2020.3033415},
timestamp = {Mon, 10 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangNLYWZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangPSTB21,
author = {Fengchao Zhang and
Shubhra Deb Paul and
Patanjali SLPSK and
Amit Ranjan Trivedi and
Swarup Bhunia},
title = {On Database-Free Authentication of Microelectronic Components},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {1},
pages = {149--161},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3039723},
doi = {10.1109/TVLSI.2020.3039723},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangPSTB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangYLLCM21,
author = {Rui Zhang and
Kexin Yang and
Zhaocheng Liu and
Taizhi Liu and
Wenshan Cai and
Linda Milor},
title = {A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability
Degradation of {SRAM} Cache Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {5},
pages = {857--870},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3056674},
doi = {10.1109/TVLSI.2021.3056674},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangYLLCM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoGLYWK21,
author = {Chenxi Zhao and
Jiawei Guo and
Huihua Liu and
Yiming Yu and
Yunqiu Wu and
Kai Kang},
title = {A 33-41-GHz SiGe-BiCMOS Digital Step Attenuator With Minimized Unit
Impedance Variation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {3},
pages = {568--579},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3046016},
doi = {10.1109/TVLSI.2020.3046016},
timestamp = {Tue, 23 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoGLYWK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaoZ21,
author = {Zhenxin Zhao and
Lihong Zhang},
title = {Efficient Performance Modeling for Automated {CMOS} Analog Circuit
Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1824--1837},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3107404},
doi = {10.1109/TVLSI.2021.3107404},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaoZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhongCJANLYL21,
author = {Hongtao Zhong and
Shengjie Cao and
Li Jiang and
Xia An and
Vijaykrishnan Narayanan and
Yongpan Liu and
Huazhong Yang and
Xueqing Li},
title = {DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical
Relays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {11},
pages = {1981--1993},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3115622},
doi = {10.1109/TVLSI.2021.3115622},
timestamp = {Wed, 15 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhongCJANLYL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouMWWOKFWC21,
author = {Jian Zhou and
Sumit K. Mandal and
Brendan L. West and
Siyuan Wei and
{\"{U}}mit Y. Ogras and
Oliver D. Kripfgans and
J. Brian Fowlkes and
Thomas F. Wenisch and
Chaitali Chakrabarti},
title = {Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging
Based on Synthetic Aperture Sequential Beamforming},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {333--346},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3035698},
doi = {10.1109/TVLSI.2020.3035698},
timestamp = {Thu, 11 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouMWWOKFWC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhouWJLW21,
author = {Bin Zhou and
Guangsen Wang and
Guisheng Jie and
Qing Liu and
Zhiwei Wang},
title = {A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1782--1789},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3105268},
doi = {10.1109/TVLSI.2021.3105268},
timestamp = {Thu, 23 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhouWJLW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuBPCCMKCSXGL21,
author = {Lingjun Zhu and
Lennart Bamberg and
Sai Surya Kiran Pentapati and
Kyungwook Chang and
Francky Catthoor and
Dragomir Milojevic and
Manu Komalan and
Brian Cline and
Saurabh Sinha and
Xiaoqing Xu and
Alberto Garc{\'{\i}}a{-}Ortiz and
Sung Kyu Lim},
title = {High-Performance Logic-on-Memory Monolithic 3-D {IC} Designs for Arm
Cortex-A Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {6},
pages = {1152--1163},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3073070},
doi = {10.1109/TVLSI.2021.3073070},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuBPCCMKCSXGL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhuangCPT21,
author = {Haoyu Zhuang and
Wenzhen Cao and
Xizhu Peng and
He Tang},
title = {A Three-Stage Comparator and Its Modified Version With Fast Speed
and Low Kickback},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {7},
pages = {1485--1489},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3077624},
doi = {10.1109/TVLSI.2021.3077624},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhuangCPT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AdetomiEA20,
author = {Adewale Adetomi and
Godwin Enemali and
Tughrul Arslan},
title = {Enabling Dynamic Communication for Runtime Circuit Relocation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {142--155},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2934927},
doi = {10.1109/TVLSI.2019.2934927},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AdetomiEA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Afzali-KushaVKP20,
author = {Hassan Afzali{-}Kusha and
Marzieh Vaeztourshizi and
Mehdi Kamal and
Massoud Pedram},
title = {Design Exploration of Energy-Efficient Accuracy-Configurable Dadda
Multipliers With Improved Lifetime Based on Voltage Overscaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1207--1220},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2978874},
doi = {10.1109/TVLSI.2020.2978874},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Afzali-KushaVKP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AgnesinaYKCYL20,
author = {Anthony Agnesina and
James Yamaguchi and
Christian Krutzik and
John Carson and
Jean Yang{-}Scharlotta and
Sung Kyu Lim},
title = {A COTS-Based Novel 3-D {DRAM} Memory Cube Architecture for Space Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {2055--2068},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3002211},
doi = {10.1109/TVLSI.2020.3002211},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AgnesinaYKCYL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AgrawalCRSSKSSL20,
author = {Amogh Agrawal and
Indranil Chakraborty and
Deboleena Roy and
Utkarsh Saxena and
Saima Sharmin and
Minsuk Koo and
Yong Shim and
Gopalakrishnan Srinivasan and
Chamika M. Liyanagedera and
Abhronil Sengupta and
Kaushik Roy},
title = {Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile
Technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2481--2494},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2991679},
doi = {10.1109/TVLSI.2020.2991679},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AgrawalCRSSKSSL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmedSB20,
author = {Ibrahim Ahmed and
Linda L. Shen and
Vaughn Betz},
title = {Optimizing {FPGA} Logic Circuitry for Variable Voltage Supplies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {890--903},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2962501},
doi = {10.1109/TVLSI.2019.2962501},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmedSB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AliRBDJOH20,
author = {Khaled Alhaj Ali and
Mostafa Rizk and
Amer Baghdadi and
Jean{-}Philippe Diguet and
Jalal Jomaah and
Naoya Onizawa and
Takahiro Hanyu},
title = {Memristive Computational Memory Using Memristor Overwrite Logic {(MOL)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2370--2382},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3011522},
doi = {10.1109/TVLSI.2020.3011522},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliRBDJOH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto20,
author = {Massimo Alioto},
title = {Editorial on the Opening of the New Editorial Year - The State of
the {IEEE} Transactions on Very Large Scale Integration {(VLSI)} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {1--2},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2955524},
doi = {10.1109/TVLSI.2019.2955524},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Alioto20a,
author = {Massimo Alioto},
title = {Editorial on the Conclusion of the 2020 Editorial Year - The Climactic
Finale of a Peculiar Year},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2479--2480},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3037376},
doi = {10.1109/TVLSI.2020.3037376},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Alioto20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AnsariMCSVH20,
author = {Mohammad Saeed Ansari and
Vojtech Mrazek and
Bruce F. Cockburn and
Luk{\'{a}}s Sekanina and
Zdenek Vas{\'{\i}}cek and
Jie Han},
title = {Improving the Accuracy and Hardware Efficiency of Neural Networks
Using Approximate Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {317--328},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2940943},
doi = {10.1109/TVLSI.2019.2940943},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AnsariMCSVH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ArandaSM20,
author = {Luis Alberto Aranda and
Alfonso S{\'{a}}nchez{-}Maci{\'{a}}n and
Juan Antonio Maestro},
title = {An Algorithmic-Based Fault Detection Technique for the 1-D Discrete
Cosine Transform},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1336--1340},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2969094},
doi = {10.1109/TVLSI.2020.2969094},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ArandaSM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AsifGHM20,
author = {Muhammad Asif and
Xiangzhou Guo and
Anyong Hu and
Jungang Miao},
title = {An FPGA-Based 1-GHz, 128 {\texttimes} 128 Cross-Correlator for Aperture
Synthesis Imaging},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {129--141},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2937990},
doi = {10.1109/TVLSI.2019.2937990},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AsifGHM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BahadoriJ20,
author = {Milad Bahadori and
Kimmo J{\"{a}}rvinen},
title = {A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies
and Functional Encryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2182--2195},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3010585},
doi = {10.1109/TVLSI.2020.3010585},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BahadoriJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaharW20,
author = {Ali Newaz Bahar and
Khan A. Wahid},
title = {Design and Implementation of Approximate {DCT} Architecture in Quantum-Dot
Cellular Automata},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2530--2539},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3013724},
doi = {10.1109/TVLSI.2020.3013724},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaharW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaiALY20,
author = {Kangjun Bai and
Qiyuan An and
Lingjia Liu and
Yang Yi},
title = {A Training-Efficient Hybrid-Structured Deep Neural Network With Reconfigurable
Memristive Synapses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {62--75},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2942267},
doi = {10.1109/TVLSI.2019.2942267},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaiALY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaileyFBWJ20,
author = {Tony Bailey and
Andrew Ford and
Siddharth Barve and
Jacob Wells and
Rashmi Jha},
title = {Development of a Short-Term to Long-Term Supervised Spiking Neural
Network Processor},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2410--2423},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3013810},
doi = {10.1109/TVLSI.2020.3013810},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaileyFBWJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BalajiCDWHDIKDS20,
author = {Adarsha Balaji and
Francky Catthoor and
Anup Das and
Yuefeng Wu and
Khanh Huynh and
Francesco Dell'Anna and
Giacomo Indiveri and
Jeffrey L. Krichmar and
Nikil D. Dutt and
Siebren Schaafsma},
title = {Mapping Spiking Neural Networks to Neuromorphic Hardware},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {76--86},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2951493},
doi = {10.1109/TVLSI.2019.2951493},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BalajiCDWHDIKDS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BanerjeeCC20,
author = {Sanmitra Banerjee and
Arjun Chaudhuri and
Krishnendu Chakrabarty},
title = {Analysis of the Impact of Process Variations and Manufacturing Defects
on the Performance of Carbon-Nanotube FETs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1513--1526},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2976734},
doi = {10.1109/TVLSI.2020.2976734},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/BanerjeeCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Bank-TavakoliGK20,
author = {Erfan Bank{-}Tavakoli and
Seyed Abolfazl Ghasemzadeh and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {{POLAR:} {A} Pipelined/Overlapped FPGA-Based {LSTM} Accelerator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {838--842},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947639},
doi = {10.1109/TVLSI.2019.2947639},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Bank-TavakoliGK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BavandpourSMS20,
author = {Mohammad Bavandpour and
Shubham Sahay and
Mohammad Reza Mahmoodi and
Dmitri B. Strukov},
title = {Efficient Mixed-Signal Neurocomputing Via Successive Integration and
Rescaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {823--827},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2946516},
doi = {10.1109/TVLSI.2019.2946516},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BavandpourSMS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BonettiGGTB20,
author = {Andrea Bonetti and
Roman Golman and
Robert Giterman and
Adam Teman and
Andreas Burg},
title = {Gain-Cell Embedded DRAMs: Modeling and Design Space},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {646--659},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2955933},
doi = {10.1109/TVLSI.2019.2955933},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BonettiGGTB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CavalcanteSZSB20,
author = {Matheus A. Cavalcante and
Fabian Schuiki and
Florian Zaruba and
Michael Schaffner and
Luca Benini},
title = {Ara: {A} 1-GHz+ Scalable and Energy-Efficient {RISC-V} Vector Processor
With Multiprecision Floating-Point Support in 22-nm {FD-SOI}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {530--543},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2950087},
doi = {10.1109/TVLSI.2019.2950087},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CavalcanteSZSB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangC20,
author = {Chia{-}Hung Chang and
Wei{-}Hsien Chen},
title = {Vital-Sign Processing Receiver With Clutter Elimination Using Servo
Feedback Loop for {UWB} Pulse Radar System},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {292--296},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2940035},
doi = {10.1109/TVLSI.2019.2940035},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCFC20,
author = {Chun{-}Chi Chen and
Chao{-}Lieh Chen and
Wei Fang and
Yen{-}Chan Chu},
title = {All-Digital {CMOS} Time-to-Digital Converter With Temperature-Measuring
Capability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {2079--2083},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3007587},
doi = {10.1109/TVLSI.2020.3007587},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCFC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenCMWCH20,
author = {Poki Chen and
Yung{-}Hsuan Chen and
John Carl Joel Salao Marquez and
Ruei{-}Ting Wang and
Jiann{-}Jong Chen and
Yuh{-}Shyan Hwang},
title = {Low Flicker Dimmable Multichannel {LED} Driver With Matrix-Style {DPWM}
and Precise Current Matching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2233--2242},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3003520},
doi = {10.1109/TVLSI.2020.3003520},
timestamp = {Sun, 11 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenCMWCH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHC20,
author = {Chun{-}Chi Chen and
Chorng{-}Sii Hwang and
Kai{-}Hsiang Chang},
title = {All-Digital Cost-Efficient {CMOS} Digital-to-Time Converter Using
Binary-Weighted Pulse Expansion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1094--1098},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2952657},
doi = {10.1109/TVLSI.2019.2952657},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenHSSLFL20,
author = {Qinyu Chen and
Yan Huang and
Rui Sun and
Wenqing Song and
Zhonghai Lu and
Yuxiang Fu and
Li Li},
title = {An Efficient Accelerator for Multiple Convolutions From the Sparsity
Perspective},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1540--1544},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2976454},
doi = {10.1109/TVLSI.2020.2976454},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenHSSLFL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLB20,
author = {Boyang Chen and
Kai Liu and
Evgeny Belyaev},
title = {An Efficient Hardware Implementation of Multialphabet Adaptive Arithmetic
Encoder Based on Generalized Virtual Sliding Window},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1326--1330},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2966306},
doi = {10.1109/TVLSI.2020.2966306},
timestamp = {Tue, 11 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLKK20,
author = {Yuzong Chen and
Lu Lu and
Bongjin Kim and
Tony Tae{-}Hyoung Kim},
title = {Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage
and Computing In-Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2636--2649},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3028848},
doi = {10.1109/TVLSI.2020.3028848},
timestamp = {Wed, 24 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLKK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenLWQMKM20,
author = {Poki Chen and
Jian{-}Ting Lan and
Ruei{-}Ting Wang and
Nguyen My Qui and
John Carl Joel Salao Marquez and
Seiji Kajihara and
Yousuke Miyake},
title = {High-Precision {PLL} Delay Matrix With Overclocking and Double Data
Rate for Accurate {FPGA} Time-to-Digital Converters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {904--913},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2962606},
doi = {10.1109/TVLSI.2019.2962606},
timestamp = {Sun, 11 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenLWQMKM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenTSPTM20,
author = {Liang Chen and
Sheldon X.{-}D. Tan and
Zeyu Sun and
Shaoyi Peng and
Min Tang and
Junfa Mao},
title = {Fast Analytic Electromigration Analysis for General Multisegment Interconnect
Wires},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {421--432},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2940197},
doi = {10.1109/TVLSI.2019.2940197},
timestamp = {Tue, 19 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenTSPTM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengCSH20,
author = {Hao{-}Yu Cheng and
Chen{-}Wei Chen and
Chung{-}An Shen and
Yuan{-}Hao Huang},
title = {The Configurable Hybrid Precoding Processor for Bit-Stream-Based mmWave
{MIMO} Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2612--2622},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3029626},
doi = {10.1109/TVLSI.2020.3029626},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengCSH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChengYF20,
author = {Yi{-}Hao Cheng and
Tao{-}Chun Yu and
Shao{-}Yun Fang},
title = {Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform
Track Resources},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1881--1892},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2985312},
doi = {10.1109/TVLSI.2020.2985312},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChengYF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChouL20,
author = {Ming{-}Han Chou and
Shen{-}Iuan Liu},
title = {A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked
Type-I {PLL}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2474--2478},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3014885},
doi = {10.1109/TVLSI.2020.3014885},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChouL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChoukseyK20,
author = {Ramanuj Chouksey and
Chandan Karfa},
title = {Verification of Scheduling of Conditional Behaviors in High-Level
Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1638--1651},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2978242},
doi = {10.1109/TVLSI.2020.2978242},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChoukseyK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CiprutF20,
author = {Albert Ciprut and
Eby G. Friedman},
title = {Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout
Regulators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {414--420},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2941967},
doi = {10.1109/TVLSI.2019.2941967},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CiprutF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CuiLW20,
author = {Hangxuan Cui and
Jun Lin and
Zhongfeng Wang},
title = {Information Storage Bit-Flipping Decoder for {LDPC} Codes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2464--2468},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3009270},
doi = {10.1109/TVLSI.2020.3009270},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CuiLW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DaneshVKRSCS20,
author = {Mohammadhadi Danesh and
Aishwarya Bahudhanam Venkatasubramaniyan and
Gaurav Kapoor and
Naveen Ramesh and
Sudarsan Sadasivuni and
Sanjeev Tannirkulam Chandrasekaran and
Arindam Sanyal},
title = {Unified Analog {PUF} and {TRNG} Based on Current-Steering {DAC} and
{VCO}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2280--2289},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3011648},
doi = {10.1109/TVLSI.2020.3011648},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DaneshVKRSCS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DangAAT20,
author = {Khanh N. Dang and
Akram Ben Ahmed and
Abderazek Ben Abdallah and
Xuan{-}Tu Tran},
title = {{TSV-OCT:} {A} Scalable Online Multiple-TSV Defects Localization for
Real-Time 3-D-IC Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {672--685},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2948878},
doi = {10.1109/TVLSI.2019.2948878},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DangAAT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DasKB20,
author = {Surajit Das and
Chandan Karfa and
Santosh Biswas},
title = {Formal Modeling of Network-on-Chip Using {CFSM} and its Application
in Detecting Deadlock},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1016--1029},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2959618},
doi = {10.1109/TVLSI.2019.2959618},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DasKB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DattaCP20,
author = {Piyali Datta and
Arpan Chakraborty and
Rajat Kumar Pal},
title = {A Predictive Model for Fluid-Control Codesign of Paper-Based Digital
Biochips Following a Machine Learning Approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2584--2597},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3030501},
doi = {10.1109/TVLSI.2020.3030501},
timestamp = {Thu, 31 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DattaCP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DavilaCCTJ20,
author = {Henry Lopez Davila and
Hsun{-}Wei Chan and
Kang{-}Lun Chiu and
Pei{-}Yun Tsai and
Shyh{-}Jye Jou},
title = {A 75-Gb/s/mm\({}^{\mbox{2}}\) and Energy-Efficient {LDPC} Decoder
Based on a Reduced Complexity Second Minimum Approximation Min-Sum
Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {926--939},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2955925},
doi = {10.1109/TVLSI.2019.2955925},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DavilaCCTJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DeKNG20,
author = {Asmit De and
Mohammad Nasim Imtiaz Khan and
Karthikeyan Nagarajan and
Swaroop Ghosh},
title = {HarTBleed: Using Hardware Trojans for Data Leakage Exploits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {968--979},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2961358},
doi = {10.1109/TVLSI.2019.2961358},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DeKNG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DengWCDJC20,
author = {Wei Deng and
Rui Wu and
Zhijie Chen and
Manlai Ding and
Haikun Jia and
Baoyong Chi},
title = {A 35-GHz {TX} and {RX} Front End With High {TX} Output Power for Ka-Band
{FMCW} Phased-Array Radar Transceivers in {CMOS} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2089--2098},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3008423},
doi = {10.1109/TVLSI.2020.3008423},
timestamp = {Fri, 02 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DengWCDJC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DhanuskodiAH20,
author = {Siva Nishok Dhanuskodi and
Samuel Allen and
Daniel E. Holcomb},
title = {Efficient Register Renaming Architectures for 8-bit {AES} Datapath
at 0.55 pJ/bit in 16-nm FinFET},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1807--1820},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2999593},
doi = {10.1109/TVLSI.2020.2999593},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DhanuskodiAH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DingKM20,
author = {Qian Ding and
Graham Knight and
Terrence S. T. Mak},
title = {An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired
Clock Distribution Network for Many-Core Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {2042--2054},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3003091},
doi = {10.1109/TVLSI.2020.3003091},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DingKM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DodoBT20,
author = {Samir Ben Dodo and
Rajendra Bishnoi and
Mehdi Baradaran Tahoori},
title = {Secure {STT-MRAM} Bit-Cell Design Resilient to Differential Power
Analysis Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {263--272},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2940449},
doi = {10.1109/TVLSI.2019.2940449},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DodoBT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongWLZAHP20,
author = {Hongxi Dong and
Manzhen Wang and
Yuanyong Luo and
Muhan Zheng and
Mengyu An and
Yajun Ha and
Hongbing Pan},
title = {{PLAC:} Piecewise Linear Approximation Computation for All Nonlinear
Unary Functions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {2014--2027},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3004602},
doi = {10.1109/TVLSI.2020.3004602},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DongWLZAHP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuLDN20,
author = {Yiran Du and
Wei Li and
Zibin Dai and
Longmei Nan},
title = {PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array
With Intelligent Mapping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1302--1315},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2972392},
doi = {10.1109/TVLSI.2020.2972392},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DuLDN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DuchQWLBCA20,
author = {Loris Duch and
Miguel Pe{\'{o}}n Quir{\'{o}}s and
Pieter Weckx and
Alexandre Levisse and
Rub{\'{e}}n Braojos and
Francky Catthoor and
David Atienza},
title = {Analysis of Functional Errors Produced by Long-Term Workload-Dependent
{BTI} Degradation in Ultralow Power Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2122--2133},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3003471},
doi = {10.1109/TVLSI.2020.3003471},
timestamp = {Mon, 20 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DuchQWLBCA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EdstromDXG20,
author = {Jonathon Edstrom and
Hritom Das and
Yiwen Xu and
Na Gong},
title = {Memory Optimization for Energy-Efficient Differentially Private Deep
Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {307--316},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2946128},
doi = {10.1109/TVLSI.2019.2946128},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EdstromDXG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErozanWBAT20,
author = {Ahmet Turan Erozan and
Guan Ying Wang and
Rajendra Bishnoi and
Jasmin Aghassi{-}Hagmann and
Mehdi Baradaran Tahoori},
title = {A Compact Low-Voltage True Random Number Generator Based on Inkjet
Printing Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1485--1495},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2975876},
doi = {10.1109/TVLSI.2020.2975876},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ErozanWBAT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErozanWFMAT20,
author = {Ahmet Turan Erozan and
Dennis D. Weller and
Yijing Feng and
Gabriel Cadilha Marques and
Jasmin Aghassi{-}Hagmann and
Mehdi B. Tahoori},
title = {A Printed Camouflaged Cell Against Reverse Engineering of Printed
Electronics Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2448--2458},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3022776},
doi = {10.1109/TVLSI.2020.3022776},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ErozanWFMAT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ErozanWRBAT20,
author = {Ahmet Turan Erozan and
Dennis D. Weller and
Farhan Rasheed and
Rajendra Bishnoi and
Jasmin Aghassi{-}Hagmann and
Mehdi Baradaran Tahoori},
title = {A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1496--1504},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2980931},
doi = {10.1109/TVLSI.2020.2980931},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ErozanWRBAT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FahimJMM20,
author = {Farah Fahim and
Siddhartha Joshi and
Seda Ogrenci{-}Memik and
Hooman Mohseni},
title = {A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration
Tree},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {576--584},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2953871},
doi = {10.1109/TVLSI.2019.2953871},
timestamp = {Mon, 31 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FahimJMM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FanLQQWLSXY20,
author = {Zichen Fan and
Zheyu Liu and
Zheng Qu and
Fei Qiao and
Qi Wei and
Xinjun Liu and
Yinan Sun and
Shuzheng Xu and
Huazhong Yang},
title = {{ASP-SIFT:} Using Analog Signal Processing Architecture to Accelerate
Keypoint Detection of {SIFT} Algorithm},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {198--211},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2936818},
doi = {10.1109/TVLSI.2019.2936818},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FanLQQWLSXY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FanZG20,
author = {Xin Fan and
Shutao Zhang and
Tobias Gemmeke},
title = {Approximation of Transcendental Functions With Guaranteed Algorithmic
QoS by Multilayer Pareto Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2495--2508},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3012008},
doi = {10.1109/TVLSI.2020.3012008},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FanZG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FarahaniBF20,
author = {Ali A. D. Farahani and
Hakem Beitollahi and
Mahmood Fathi},
title = {A Dynamic General Accelerator for Integer and Fixed-Point Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2509--2517},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3023106},
doi = {10.1109/TVLSI.2020.3023106},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FarahaniBF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FaraoneKHZLBL20,
author = {Julian Faraone and
Martin Kumm and
Martin Hardieck and
Peter Zipf and
Xueyuan Liu and
David Boland and
Philip H. W. Leong},
title = {AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {115--128},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2939429},
doi = {10.1109/TVLSI.2019.2939429},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/FaraoneKHZLBL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FathiMA20,
author = {Amir Fathi and
Behbood Mashoufi and
Sarkis Azizian},
title = {Very Fast, High-Performance 5-2 and 7-2 Compressors in {CMOS} Process
for Rapid Parallel Accumulations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1403--1412},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2983458},
doi = {10.1109/TVLSI.2020.2983458},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FathiMA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FlorosES20,
author = {George Floros and
Nestor E. Evmorfopoulos and
Georgios I. Stamoulis},
title = {Frequency-Limited Reduction of Regular and Singular Circuit Models
Via Extended Krylov Subspace Method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1610--1620},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2994534},
doi = {10.1109/TVLSI.2020.2994534},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FlorosES20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FordjourRS20,
author = {Samuel Annor Fordjour and
Joseph Riad and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {A 175.2-mW 4-Stage {OTA} With Wide Load Range {(400} pF-12 nF) Using
Active Parallel Compensation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1621--1629},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2993059},
doi = {10.1109/TVLSI.2020.2993059},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FordjourRS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuL20,
author = {Kuan{-}Lin Fu and
Shen{-}Iuan Liu},
title = {A 64-Gb/s {PAM-4} Optical Receiver With Amplitude/Phase Correction
and Threshold Voltage/Data Level Calibration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1726--1735},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2991721},
doi = {10.1109/TVLSI.2020.2991721},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FuL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FuLLWSW20,
author = {Yupeng Fu and
Lianming Li and
Yilong Liao and
Xuan Wang and
Yongjian Shi and
Dongming Wang},
title = {A 32-GHz Nested-PLL-Based {FMCW} Modulator With 2.16-GHz Bandwidth
in a 65-nm {CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1600--1609},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2992123},
doi = {10.1109/TVLSI.2020.2992123},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FuLLWSW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GaoZYGXR20,
author = {Zhen Gao and
Lingling Zhang and
Tong Yan and
Kangkang Guo and
Zhan Xu and
Pedro Reviriego},
title = {Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2563--2572},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3016976},
doi = {10.1109/TVLSI.2020.3016976},
timestamp = {Thu, 21 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GaoZYGXR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GarnicaLH20,
author = {Oscar Garnica and
Juan Lanchares and
Jos{\'{e}} Ignacio Hidalgo},
title = {Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based
Reconfigurable Designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {914--925},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2961782},
doi = {10.1109/TVLSI.2019.2961782},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GarnicaLH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GennaroSM20,
author = {Alessandro de Gennaro and
Danil Sokolov and
Andrey Mokhov},
title = {Design and Implementation of Reconfigurable Asynchronous Pipelines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1527--1539},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2975591},
doi = {10.1109/TVLSI.2020.2975591},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GennaroSM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GhandaliMMP20,
author = {Samaneh Ghandali and
Thorben Moos and
Amir Moradi and
Christof Paar},
title = {Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1435--1448},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2982473},
doi = {10.1109/TVLSI.2020.2982473},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GhandaliMMP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GolanbariKOGT20,
author = {Mohammad Saber Golanbari and
Saman Kiamehr and
Fabian Oboril and
Anteneh Gebregiorgis and
Mehdi Baradaran Tahoori},
title = {Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication
Calibration and Adaptation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {443--455},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2945026},
doi = {10.1109/TVLSI.2019.2945026},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GolanbariKOGT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuiTTLG20,
author = {Xiaoyan Gui and
Bingjun Tang and
Renjie Tang and
Dan Li and
Li Geng},
title = {Low-Supply Sensitivity {LC} VCOs With Complementary Varactors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1589--1599},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2991765},
doi = {10.1109/TVLSI.2020.2991765},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/GuiTTLG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GulerJ20,
author = {Abdullah Guler and
Niraj K. Jha},
title = {McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework
for 3-D Hybrid Monolithic Multicore Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2146--2156},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3002723},
doi = {10.1109/TVLSI.2020.3002723},
timestamp = {Thu, 17 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GulerJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hadjitheophanous20,
author = {Stavros Hadjitheophanous and
Stelios N. Neophytou and
Maria K. Michael},
title = {Maintaining Scalability of Test Generation Using Multicore Shared
Memory Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {553--564},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947183},
doi = {10.1109/TVLSI.2019.2947183},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hadjitheophanous20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanCHZ20,
author = {Yuanyuan Han and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T {SRAM} and Peripheral
Circuit in 28-nm Technology for Space Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1089--1093},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2961736},
doi = {10.1109/TVLSI.2019.2961736},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HanCHZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HasibST20,
author = {Omar Al{-}Terkawi Hasib and
Yvon Savaria and
Claude Thibeault},
title = {Optimization of Small-Delay Defects Test Quality by Clock Speed Selection
and Proper Masking Based on the Weighted Slack Percentage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {764--776},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2949037},
doi = {10.1109/TVLSI.2019.2949037},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HasibST20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeZJ20,
author = {Guanghui He and
Sijie Zheng and
Naifeng Jing},
title = {A Hierarchical Scrubbing Technique for {SEU} Mitigation on SRAM-Based
FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2134--2145},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3010647},
doi = {10.1109/TVLSI.2020.3010647},
timestamp = {Mon, 20 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeZJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeZL20,
author = {Guanghui He and
Xiaoyu Zhang and
Zhuojun Liang},
title = {Algorithm and Architecture of an Efficient {MIMO} Detector With Cross-Level
Parallel Tree-Search},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {467--479},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947495},
doi = {10.1109/TVLSI.2019.2947495},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeZL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hoff20,
author = {James R. Hoff},
title = {Conflux - An Asynchronous Two-to-One Multiplexor for Time-Division
Multiplexing and Clockless, Tokenless Readout},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {503--515},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2942820},
doi = {10.1109/TVLSI.2019.2942820},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hoff20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangL20,
author = {Chung{-}Hsun Huang and
Wei{-}Chen Liao},
title = {A High-Performance {LDO} Regulator Enabling Low-Power SoC With Voltage
Scaling Approaches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1141--1149},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2972904},
doi = {10.1109/TVLSI.2020.2972904},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IoannouAF20,
author = {Lenos Ioannou and
Abdullah Al{-}Dujaili and
Suhaib A. Fahmy},
title = {High Throughput Spatial Convolution Filters on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1392--1402},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2987202},
doi = {10.1109/TVLSI.2020.2987202},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/IoannouAF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IrfanUCC20,
author = {Muhammad Irfan and
Zahid Ullah and
Mehdi Hasan Chowdhury and
Ray C. C. Cheung},
title = {{RPE-TCAM:} Reconfigurable Power-Efficient Ternary Content-Addressable
Memory on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1925--1929},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2993168},
doi = {10.1109/TVLSI.2020.2993168},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/IrfanUCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IsgencMZPP20,
author = {Mehmet Meric Isgenc and
Mayler G. A. Martins and
V. Mohammed Zackriya and
Samuel N. Pagliarini and
Lawrence T. Pileggi},
title = {Logic {IP} for Low-Cost {IC} Design in Advanced {CMOS} Nodes},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {585--595},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2942825},
doi = {10.1109/TVLSI.2019.2942825},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IsgencMZPP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainGR20,
author = {Shubham Jain and
Sumeet Kumar Gupta and
Anand Raghunathan},
title = {TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1567--1577},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2993045},
doi = {10.1109/TVLSI.2020.2993045},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JainGR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JainLA20,
author = {Saurabh Jain and
Longyang Lin and
Massimo Alioto},
title = {Automated Design of Reconfigurable Microarchitectures for Accelerators
Under Wide-Voltage Scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {777--790},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2950959},
doi = {10.1109/TVLSI.2019.2950959},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JainLA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Jamshidi20,
author = {Vahid Jamshidi},
title = {A {VLSI} Majority-Logic Device Based on Spin Transfer Torque Mechanism
for Brain-Inspired Computing Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1858--1866},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2997369},
doi = {10.1109/TVLSI.2020.2997369},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Jamshidi20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JangK20,
author = {Sung{-}Joon Jang and
Chong{-}Min Kyung},
title = {Resource-Efficient and High-Throughput {VLSI} Design of Global Optical
Flow Method for Mobile Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1717--1725},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2984822},
doi = {10.1109/TVLSI.2020.2984822},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JangK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JangP20,
author = {Sungmin Jang and
Jaeyoung Park},
title = {{HYFII:} HYbrid Fault Injection Infrastructure for Accurate Runtime
System Failure Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1893--1900},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2992982},
doi = {10.1109/TVLSI.2020.2992982},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JangP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JavvajiT20,
author = {Pavan Kumar Javvaji and
Spyros Tragoudas},
title = {Test Pattern Generation and Critical Path Selection in the Presence
of Statistical Delays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {163--173},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2941426},
doi = {10.1109/TVLSI.2019.2941426},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JavvajiT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JayasankaranSAS20,
author = {Nithyashankari Gummidipoondi Jayasankaran and
Adriana C. Sanabria{-}Borbon and
Amr Abuellil and
Edgar S{\'{a}}nchez{-}Sinencio and
Jiang Hu and
Jeyavijayan Rajendran},
title = {Breaking Analog Locking Techniques},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2157--2170},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3007159},
doi = {10.1109/TVLSI.2020.3007159},
timestamp = {Wed, 07 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JayasankaranSAS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JiSZYZ20,
author = {Chao Ji and
Yifei Shen and
Zaichen Zhang and
Xiaohu You and
Chuan Zhang},
title = {Autogeneration of Pipelined Belief Propagation Polar Decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1703--1716},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2983975},
doi = {10.1109/TVLSI.2020.2983975},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JiSZYZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JooLJKYKJ20,
author = {Hye{-}Yoon Joo and
Jinhyung Lee and
Haram Ju and
Han{-}Gon Ko and
Jungmin Yoon and
Byungjun Kang and
Deog{-}Kyoon Jeong},
title = {A Maximum-Eye-Tracking {CDR} With Biased Data-Level and Eye Slope
Detector for Near-Optimal Timing Adaptation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2708--2720},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3029079},
doi = {10.1109/TVLSI.2020.3029079},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JooLJKYKJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoshiSS20,
author = {Ashish Joshi and
Hitesh Shrimali and
Satinder K. Sharma},
title = {A Discrete-Time {MOS} Parametric Amplifier-Based Chopped Signal Demodulator},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2268--2279},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3015947},
doi = {10.1109/TVLSI.2020.3015947},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoshiSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JuL20,
author = {Hyungyu Ju and
Minjae Lee},
title = {A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage
Operational Amplifiers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1770--1781},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2986508},
doi = {10.1109/TVLSI.2020.2986508},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/JuL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Kalanadhabhatta20,
author = {Srisubha Kalanadhabhatta and
Deepak Kumar and
Kiran Kumar Anumandla and
S. Ashish Reddy and
Amit Acharyya},
title = {PUF-Based Secure Chaotic Random Number Generator Design Methodology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1740--1744},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2979269},
doi = {10.1109/TVLSI.2020.2979269},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Kalanadhabhatta20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KalipatnapuC20,
author = {Shantharam Kalipatnapu and
Indrajit Chakrabarti},
title = {Low-Complexity Interval Passing Algorithm and {VLSI} Architecture
for Binary Compressed Sensing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1283--1291},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2967477},
doi = {10.1109/TVLSI.2020.2967477},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KalipatnapuC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KandpalTAS20,
author = {Jyoti Kandpal and
Abhishek Tomar and
Mayur Agarwal and
Kamal Kumar Sharma},
title = {High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T {XOR-XNOR}
Cell},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1413--1422},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2983850},
doi = {10.1109/TVLSI.2020.2983850},
timestamp = {Wed, 12 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KandpalTAS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KannoTSK20,
author = {Yusuke Kanno and
Tadanobu Toba and
Kotaro Shimamura and
Nobuyasu Kanekawa},
title = {Design Method for Online Totally Self-Checking Comparators Implementable
on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {726--735},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2946180},
doi = {10.1109/TVLSI.2019.2946180},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KannoTSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarGBRB20,
author = {Bapi Kar and
Pradeep Kumar Gopalakrishnan and
Sumon Kumar Bose and
Mohendra Roy and
Arindam Basu},
title = {{ADIC:} Anomaly Detection Integrated Circuit in 65-nm {CMOS} Utilizing
Approximate Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2518--2529},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3016939},
doi = {10.1109/TVLSI.2020.3016939},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarGBRB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhanDG20,
author = {Mohammad Nasim Imtiaz Khan and
Asmit De and
Swaroop Ghosh},
title = {Cache-Out: Leaking Cache Memory Using Hardware Trojan},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1461--1470},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2982188},
doi = {10.1109/TVLSI.2020.2982188},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KhanDG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimLK20,
author = {Tae Hyun Kim and
Hayoung Lee and
Sungho Kang},
title = {GPU-Based Redundancy Analysis Using Concurrent Evaluation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {805--817},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2954549},
doi = {10.1109/TVLSI.2019.2954549},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimLK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimMPQKCRDSLTRS20,
author = {Jinwoo Kim and
Gauthaman Murali and
Heechun Park and
Eric Qin and
Hyoukjun Kwon and
Venkata Chaitanya Krishna Chekuri and
Nael Mizanur Rahman and
Nihar Dasari and
Arvind Singh and
Minah Lee and
Hakki Mert Torun and
Kallol Roy and
Madhavan Swaminathan and
Saibal Mukhopadhyay and
Tushar Krishna and
Sung Kyu Lim},
title = {Architecture, Chip, and Package Codesign Flow for Interposer-Based
2.5-D Chiplet Integration Enabling Heterogeneous {IP} Reuse},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2424--2437},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3015494},
doi = {10.1109/TVLSI.2020.3015494},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimMPQKCRDSLTRS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimY20,
author = {Hyochang Kim and
Changsik Yoo},
title = {A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap
Decision-Feedback Equalizer in 28-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1107--1117},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2971558},
doi = {10.1109/TVLSI.2020.2971558},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KojimaDA20,
author = {Takuya Kojima and
Nguyen Anh Vu Doan and
Hideharu Amano},
title = {GenMap: {A} Genetic Algorithmic Approach for Optimizing Spatial Mapping
of Coarse-Grained Reconfigurable Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2383--2396},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3009225},
doi = {10.1109/TVLSI.2020.3009225},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KojimaDA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KonstantinouPND20,
author = {Dimitrios Konstantinou and
Anastasios Psarras and
Chrysostomos Nicopoulos and
Giorgos Dimitrakopoulos},
title = {The Mesochronous Dual-Clock {FIFO} Buffer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {302--306},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2946348},
doi = {10.1109/TVLSI.2019.2946348},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KonstantinouPND20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KrylovF20,
author = {Gleb Krylov and
Eby G. Friedman},
title = {Design Methodology for Distributed Large-Scale {ERSFQ} Bias Networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2438--2447},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3023054},
doi = {10.1109/TVLSI.2020.3023054},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KrylovF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KulejK20,
author = {Tomasz Kulej and
Fabian Khateb},
title = {A Compact 0.3-V Class {AB} Bulk-Driven {OTA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {224--232},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2937206},
doi = {10.1109/TVLSI.2019.2937206},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KulejK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarABFS20,
author = {Binod Kumar and
Jay Adhaduk and
Kanad Basu and
Masahiro Fujita and
Virendra Singh},
title = {A Methodology to Capture Fine-Grained Internal Visibility During Multisession
Silicon Debug},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1002--1015},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2958989},
doi = {10.1109/TVLSI.2019.2958989},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarABFS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarDS20,
author = {A. R. Aravinth Kumar and
Ashudeb Dutta and
Bibhu Datta Sahoo},
title = {A Low-Power Reconfigurable Narrowband/Wideband {LNA} for Cognitive
Radio-Wireless Sensor Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {212--223},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2939708},
doi = {10.1109/TVLSI.2019.2939708},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarDS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumariH20,
author = {Meera Kumari and
S. M. Rezaul Hasan},
title = {A Low Duty Cycle Burst-Mode Telemeter Signal Generation Technique
for {VHF} Insect Tracking and Its {CMOS} Implementation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {833--837},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947696},
doi = {10.1109/TVLSI.2019.2947696},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumariH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KwonIPY20,
author = {Taehyun Kwon and
Muhammad Imran and
David Z. Pan and
Joon{-}Sung Yang},
title = {Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network
Power Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1256--1268},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2966912},
doi = {10.1109/TVLSI.2020.2966912},
timestamp = {Thu, 27 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KwonIPY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KyeKLJ20,
author = {Chan{-}Ho Kye and
Han{-}Gon Ko and
Jinhyung Lee and
Deog{-}Kyoon Jeong},
title = {A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With
Time-Based Feedforward Equalization in a 28-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1099--1106},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2965565},
doi = {10.1109/TVLSI.2020.2965565},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KyeKLJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LaiCCH20,
author = {Bo{-}Cheng Lai and
Bo{-}Ya Chen and
Bo{-}En Chen and
Yi{-}Da Hsin},
title = {{REMAP+:} An Efficient Banking Architecture for Multiple Writes of
Algorithmic Memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {660--671},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2957455},
doi = {10.1109/TVLSI.2019.2957455},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LaiCCH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LateYA20,
author = {Even L{\aa}te and
Trond Ytterdal and
Snorre Aunet},
title = {Benefiting From State Dependencies in Asymmetric {SRAM} Cells Through
Conditional Word-Flipping},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2223--2227},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3013139},
doi = {10.1109/TVLSI.2020.3013139},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LateYA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Lavalle-AvilesS20,
author = {Fernando Lavalle{-}Aviles and
Edgar S{\'{a}}nchez{-}Sinencio},
title = {A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff
Frequency Selection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1757--1769},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2999414},
doi = {10.1109/TVLSI.2020.2999414},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Lavalle-AvilesS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeYKBBK20,
author = {Van Loi Le and
Taegeun Yoo and
Ju Eon Kim and
Ngoc Le Ba and
Kwang{-}Hyun Baek and
Tony Tae{-}Hyoung Kim},
title = {A 137-{\(\mu\)}W 1.78-mm\({}^{\mbox{2}}\) 30-Frames/s Real-Time Gesture
Recognition SoC for Smart Devices},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1909--1919},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2997700},
doi = {10.1109/TVLSI.2020.2997700},
timestamp = {Thu, 27 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeYKBBK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeJWW20,
author = {Albert Lee and
Raahul Jagannathan and
Di Wu and
Kang L. Wang},
title = {A 2-D Calibration Scheme for Resistive Nonvolatile Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1371--1377},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2975589},
doi = {10.1109/TVLSI.2020.2975589},
timestamp = {Tue, 11 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeJWW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCHLT20,
author = {Zhiqun Li and
Guoxiao Cheng and
Tingting Han and
Zhennan Li and
Mi Tian},
title = {A 23-36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts
{VCO} Array in SiGe BiCMOS for 5G Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2243--2256},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3014962},
doi = {10.1109/TVLSI.2020.3014962},
timestamp = {Tue, 11 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCHLT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiDWC20,
author = {He Li and
James J. Davis and
John Wickerson and
George A. Constantinides},
title = {architect: Arbitrary-Precision Hardware With Digit Elision for Efficient
Iterative Compute},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {516--529},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2945257},
doi = {10.1109/TVLSI.2019.2945257},
timestamp = {Thu, 10 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiDWC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiEKT20,
author = {Shizhong Li and
Kamal El{-}Sankary and
Alireza Karami and
Dmitri V. Truhachev},
title = {Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput
Fiber-Optical Communications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {843--847},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2950129},
doi = {10.1109/TVLSI.2019.2950129},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiEKT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiLZD20,
author = {Xin Li and
Zhi Li and
Wei Zhou and
Zhemin Duan},
title = {Accurate On-Chip Temperature Sensing for Multicore Processors Using
Embedded Thermal Sensors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2328--2341},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3012833},
doi = {10.1109/TVLSI.2020.3012833},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiLZD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiPW20,
author = {Tso{-}Wei Li and
Jong Seok Park and
Hua Wang},
title = {A 2-24-GHz 360{\textdegree} Full-Span Differential Vector Modulator
Phase Rotator With Transformer-Based Poly-Phase Quadrature Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2623--2635},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3017707},
doi = {10.1109/TVLSI.2020.3017707},
timestamp = {Wed, 28 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiPW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiTXMWW20,
author = {Haoran Li and
Zhongyuan Tian and
Jiang Xu and
Rafael K. V. Maeda and
Zhehui Wang and
Zhifei Wang},
title = {Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware
Manycore Systems Using Reinforcement Learning},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1150--1163},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2966866},
doi = {10.1109/TVLSI.2020.2966866},
timestamp = {Wed, 02 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiTXMWW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWMLSZ20,
author = {Gang Li and
Pengjun Wang and
Xuejiao Ma and
Jiana Lian and
Junpeng Shu and
Yuejun Zhang},
title = {A 215-F{\({^2}\)} Bistable Physically Unclonable Function With an
{ACF} of {\textless}0.005 and a Native Bit Instability of 2.05{\%}
in 65-nm {CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2290--2299},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3014892},
doi = {10.1109/TVLSI.2020.3014892},
timestamp = {Tue, 06 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWMLSZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiXJZ20,
author = {Kan Li and
Xiao Xiao and
Xiangliang Jin and
Yuanjin Zheng},
title = {A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique
in 0.18- m {CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {403--413},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947534},
doi = {10.1109/TVLSI.2019.2947534},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiXJZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZ20,
author = {Diwei Li and
Dixian Zhao},
title = {High-Throughput Low-Power Area-Efficient Outphasing Modulator Based
on Unrolled and Pipelined Radix-2 {CORDIC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {480--491},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2946199},
doi = {10.1109/TVLSI.2019.2946199},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiZH20,
author = {Yin Li and
Yu Zhang and
Wei He},
title = {Fast Hybrid Karatsuba Multiplier for Type {II} Pentanomials},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2459--2463},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3021195},
doi = {10.1109/TVLSI.2020.3021195},
timestamp = {Wed, 28 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiZH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangCK20,
author = {Tung{-}Che Liang and
Krishnendu Chakrabarty and
Ramesh Karri},
title = {Programmable Daisychaining of Microelectrodes to Secure Bioassay {IP}
in {MEDA} Biochips},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1269--1282},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2967029},
doi = {10.1109/TVLSI.2020.2967029},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangCK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinCC20,
author = {Yu{-}Sheng Lin and
Wei{-}Chao Chen and
Shao{-}Yi Chien},
title = {{MERIT:} Tensor Transform for Memory-Efficient Vision Processing on
Parallel Architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {791--804},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2953171},
doi = {10.1109/TVLSI.2019.2953171},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinCC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinT20,
author = {Yu{-}Chuan Lin and
Hen{-}Wai Tsao},
title = {A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations
in 65-nm {CMOS}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {23--34},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2935305},
doi = {10.1109/TVLSI.2019.2935305},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinW20,
author = {Dave Y.{-}W. Lin and
Charles H.{-}P. Wen},
title = {{DAD-FF:} Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate
Reduction},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1030--1042},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2962080},
doi = {10.1109/TVLSI.2019.2962080},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinWPWLC20,
author = {Zhiting Lin and
Yong Wang and
Chunyu Peng and
Xiulong Wu and
Xuan Li and
Junning Chen},
title = {Multiple Sharing 7T1R Nonvolatile {SRAM} With an Improved Read/Write
Margin and Reliable Restore Yield},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {607--619},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2953005},
doi = {10.1109/TVLSI.2019.2953005},
timestamp = {Mon, 27 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinWPWLC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinZLPLWC20,
author = {Zhiting Lin and
Honglan Zhan and
Xuan Li and
Chunyu Peng and
Wenjuan Lu and
Xiulong Wu and
Junning Chen},
title = {In-Memory Computing With Double Word Lines and Three Read Ports for
Four Operands},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1316--1320},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2976099},
doi = {10.1109/TVLSI.2020.2976099},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinZLPLWC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuSZ20,
author = {Yizhong Liu and
Tian Song and
Yiqi Zhuang},
title = {A High-Throughput Subspace Pursuit Processor for {ECG} Recovery in
Compressed Sensing Using Square-Root-Free {MGS} {QR} Decomposition},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {174--187},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2936867},
doi = {10.1109/TVLSI.2019.2936867},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuSZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuXLZY20,
author = {Maliang Liu and
Jinhai Xiao and
Peng Luo and
Zhangming Zhu and
Yintang Yang},
title = {Ultrawideband Power-Switchable Transmitter With 17.7-dBm Output Power
for See-Through-Wall Radar},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1331--1335},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2972687},
doi = {10.1109/TVLSI.2020.2972687},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuXLZY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuYJWZGDZLXLL20,
author = {Chao Liu and
Jianguo Yang and
Pengfei Jiang and
Qiao Wang and
Donglin Zhang and
Tiancheng Gong and
Qingting Ding and
Yuling Zhao and
Qing Luo and
Xiaoyong Xue and
Hangbing Lv and
Ming Liu},
title = {A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation
Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2469--2473},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3019524},
doi = {10.1109/TVLSI.2020.3019524},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuYJWZGDZLXLL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuPLY20,
author = {Anni Lu and
Xiaochen Peng and
Yandong Luo and
Shimeng Yu},
title = {Benchmark of the Compute-in-Memory-Based {DNN} Accelerator With Area
Constraint},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {1945--1952},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3001526},
doi = {10.1109/TVLSI.2020.3001526},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuPLY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuYHSHY20,
author = {Shyue{-}Kung Lu and
Shu{-}Chi Yu and
Chun{-}Lung Hsu and
Chi{-}Tien Sun and
Masaki Hashizume and
Hiroyuki Yotsuyanagi},
title = {Fault-Aware Dependability Enhancement Techniques for Flash Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {634--645},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2957830},
doi = {10.1109/TVLSI.2019.2957830},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuYHSHY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuYLK20,
author = {Lu Lu and
Taegeun Yoo and
Van Loi Le and
Tony Tae{-}Hyoung Kim},
title = {A 0.506-pJ 16-kb 8T {SRAM} With Vertical Read Wordlines and Selective
Dual Split Power Lines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1345--1356},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2956232},
doi = {10.1109/TVLSI.2019.2956232},
timestamp = {Tue, 03 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LuYLK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ManasiSS20,
author = {Susmita Dey Manasi and
Farhana Sharmin Snigdha and
Sachin S. Sapatnekar},
title = {NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning
of {CNN} Computations on Cloud-Connected Mobile Clients},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1844--1857},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2995135},
doi = {10.1109/TVLSI.2020.2995135},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ManasiSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MandalDHM20,
author = {Sudipa Mandal and
Pallab Dasgupta and
Aritra Hazra and
Chunduri Rama Mohan},
title = {Assertions for Protecting Mixed-Signal Latency Contracts in Power
Management},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1745--1756},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3002481},
doi = {10.1109/TVLSI.2020.3002481},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MandalDHM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MannZKCPKHVC20,
author = {Randy W. Mann and
Meixiong Zhao and
Oh Sung Kwon and
Xi Cao and
Sanjay Parihar and
Muhammed Ahosan Ul Karim and
Jack M. Higman and
Joseph Versaggi and
Rick Carter},
title = {Bias-Dependent Variation in FinFET {SRAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1341--1344},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2974202},
doi = {10.1109/TVLSI.2020.2974202},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MannZKCPKHVC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaoLW20,
author = {Wendong Mao and
Jun Lin and
Zhongfeng Wang},
title = {{F-DNA:} Fast Convolution Architecture for Deconvolutional Network
Acceleration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1867--1880},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3000519},
doi = {10.1109/TVLSI.2020.3000519},
timestamp = {Fri, 21 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MaoLW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaragkoudakiP20,
author = {Eleni Maragkoudaki and
Vasilis F. Pavlidis},
title = {Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2551--2562},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3018062},
doi = {10.1109/TVLSI.2020.3018062},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaragkoudakiP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MathewSVM20,
author = {Libin K. Mathew and
Shanker Shreejith and
A. Prasad Vinod and
A. S. Madhukumar},
title = {A Power-Efficient Spectrum-Sensing Scheme Using 1-Bit Quantizer and
Modified Filter Banks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {2074--2078},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3009430},
doi = {10.1109/TVLSI.2020.3009430},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MathewSVM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MertOS20,
author = {Ahmet Can Mert and
Erdin{\c{c}} {\"{O}}zt{\"{u}}rk and
Erkay Savas},
title = {Design and Implementation of Encryption/Decryption Architectures for
{BFV} Homomorphic Encryption Scheme},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {353--362},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2943127},
doi = {10.1109/TVLSI.2019.2943127},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MertOS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoghaddasiSK20,
author = {Iraj Moghaddasi and
Mostafa E. Salehi and
Mehdi Kargahi},
title = {Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis
for Embedded Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {433--442},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947757},
doi = {10.1109/TVLSI.2019.2947757},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoghaddasiSK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MohantyM20,
author = {Basant Kumar Mohanty and
Pramod Kumar Meher},
title = {An Efficient Parallel DA-Based Fixed-Width Design for Approximate
Inner-Product Computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1221--1229},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2972772},
doi = {10.1109/TVLSI.2020.2972772},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MohantyM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoosMR20,
author = {Thorben Moos and
Amir Moradi and
Bastian Richter},
title = {Static Power Side-Channel Analysis - An Investigation of Measurement
Factors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {376--389},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2948141},
doi = {10.1109/TVLSI.2019.2948141},
timestamp = {Mon, 10 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MoosMR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MorenoORM20,
author = {Adri{\'{a}}n Alcolea Morena and
Javier Olivito and
Javier Resano and
Hortensia Mecha},
title = {Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {1993--2003},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3005451},
doi = {10.1109/TVLSI.2020.3005451},
timestamp = {Mon, 02 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MorenoORM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MosalmaniKS20,
author = {Alireza Mosalmani and
Mehdi Khoee and
Omid Shoaei},
title = {A 9-Bit 70-MS/s Two-Stage {SAR} {ADC} With Passive Residue Transfer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1185--1194},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2974573},
doi = {10.1109/TVLSI.2020.2974573},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MosalmaniKS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MukimDMSMBB20,
author = {Prashansa Mukim and
Aditya Dalakoti and
David McCarthy and
Carrie Segal and
Merritt Miller and
James F. Buckwalter and
Forrest Brewer},
title = {Design and Analysis of Collective Pulse Oscillators},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1242--1255},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2959532},
doi = {10.1109/TVLSI.2019.2959532},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MukimDMSMBB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MurrayLWMWHYCKA20,
author = {Kevin E. Murray and
Jason Luu and
Matthew J. P. Walker and
Conor McCullough and
Sen Wang and
Safeen Huda and
Bo Yan and
Charles Chiasson and
Kenneth B. Kent and
Jason Helge Anderson and
Jonathan Rose and
Vaughn Betz},
title = {Optimizing {FPGA} Logic Block Architectures for Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1378--1391},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2965772},
doi = {10.1109/TVLSI.2020.2965772},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MurrayLWMWHYCKA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MusavvirCKKP20,
author = {Shouvik Musavvir and
Anwesha Chatterjee and
Ryan Gary Kim and
Dae Hyun Kim and
Partha Pratim Pande},
title = {Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space
Exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {686--699},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2954770},
doi = {10.1109/TVLSI.2019.2954770},
timestamp = {Fri, 15 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MusavvirCKKP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NiLXHLY20,
author = {Tianming Ni and
Dongsheng Liu and
Qi Xu and
Zhengfeng Huang and
Huaguo Liang and
Aibin Yan},
title = {Architecture of Cobweb-Based Redundant {TSV} for Clustered Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1736--1739},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2995094},
doi = {10.1109/TVLSI.2020.2995094},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NiLXHLY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OnizawaMTYFH20,
author = {Naoya Onizawa and
Shogo Mukaida and
Akira Tamakoshi and
Hitoshi Yamagata and
Hiroyuki Fujita and
Takahiro Hanyu},
title = {High-Throughput/Low-Energy MTJ-Based True Random Number Generator
Using a Multi-Voltage/Current Converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2171--2181},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3005413},
doi = {10.1109/TVLSI.2020.3005413},
timestamp = {Mon, 20 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/OnizawaMTYFH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PalPKG20,
author = {Saptadeep Pal and
Daniel Petrisko and
Rakesh Kumar and
Puneet Gupta},
title = {Design Space Exploration for Chiplet-Assembly-Based Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1062--1073},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2968904},
doi = {10.1109/TVLSI.2020.2968904},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PalPKG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PaliwalYAG20,
author = {Pallavi Paliwal and
Vivek Yadav and
Zeeshan Ali and
Shalabh Gupta},
title = {A Fast Settling Fractional-N {DPLL} With Loop-Order Switching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {714--725},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2956100},
doi = {10.1109/TVLSI.2019.2956100},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PaliwalYAG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PanMCM20,
author = {Dashan Pan and
Chao Ma and
Lanqi Cheng and
Hao Min},
title = {A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed
Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {243--251},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2934899},
doi = {10.1109/TVLSI.2019.2934899},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PanMCM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PanWLY20,
author = {Quan Pan and
Li Wang and
Xiongshi Luo and
C. Patrick Yue},
title = {A Low-Power {PAM4} Receiver With an Adaptive Variable-Gain Rectifier-Based
Decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2099--2108},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3008199},
doi = {10.1109/TVLSI.2020.3008199},
timestamp = {Fri, 19 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PanWLY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PandeyBCR20,
author = {Pramesh Pandey and
Prabal Basu and
Koushik Chakraborty and
Sanghamitra Roy},
title = {GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience
of a Near-Threshold Tensor Processing Unit},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1557--1566},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2985057},
doi = {10.1109/TVLSI.2020.2985057},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/PandeyBCR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkAJ20,
author = {Hyun Kook Park and
Hong Keun Ahn and
Seong{-}Ook Jung},
title = {A Novel Matchline Scheduling Method for Low-Power and Reliable Search
Operation in Cross-Point-Array Nonvolatile Ternary {CAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2650--2657},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3027254},
doi = {10.1109/TVLSI.2020.3027254},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkAJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkCLT20,
author = {Jungmin Park and
Seongjoon Cho and
Taejin Lim and
Mark M. Tehranipoor},
title = {{QEC:} {A} Quantum Entropy Chip and Its Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1471--1484},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2975091},
doi = {10.1109/TVLSI.2020.2975091},
timestamp = {Tue, 30 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkCLT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkLKKJKL20,
author = {Jin Woo Park and
Hyokeun Lee and
Boyeal Kim and
Dong{-}Goo Kang and
Seung Oh Jin and
Hyun Kim and
Hyuk{-}Jae Lee},
title = {A Low-Cost and High-Throughput {FPGA} Implementation of the Retinex
Algorithm for Real-Time Video Enhancement},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {101--114},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2936260},
doi = {10.1109/TVLSI.2019.2936260},
timestamp = {Wed, 22 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkLKKJKL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParkOJ20,
author = {Juhyun Park and
Tae Woo Oh and
Seong{-}Ook Jung},
title = {pMOS Pass Gate Local Bitline {SRAM} Architecture With Virtual {\textdollar}V{\_}\{{\textbackslash}mathrm\{SS\}\}{\textdollar}
for Near-Threshold Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1079--1083},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2963704},
doi = {10.1109/TVLSI.2019.2963704},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ParkOJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pastuszak20,
author = {Grzegorz Pastuszak},
title = {Multisymbol Architecture of the Entropy Coder for {H.265/HEVC} Video
Encoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2573--2583},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3016386},
doi = {10.1109/TVLSI.2020.3016386},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pastuszak20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PereiraAV20,
author = {Marco Silva Pereira and
M{\'{a}}rio Assun{\c{c}}{\~{a}}o and
Jo{\~{a}}o Caldinhas Vaz},
title = {Analysis and Design of Current Mode Class-D Power Amplifiers With
Finite Feeding Inductors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1292--1301},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2971955},
doi = {10.1109/TVLSI.2020.2971955},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PereiraAV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PhoonLWYG20,
author = {Jun{-}Hoe Phoon and
Wai{-}Kong Lee and
Denis Chee{-}Keong Wong and
Wun{-}She Yap and
Bok{-}Min Goi},
title = {Area-Time-Efficient Code-Based Postquantum Key Encapsulation Mechanism
on {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2672--2684},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3025046},
doi = {10.1109/TVLSI.2020.3025046},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PhoonLWYG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PogueN20,
author = {Trevor E. Pogue and
Nicola Nicolici},
title = {Incremental Fault Analysis: Relaxing the Fault Model of Differential
Fault Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {3},
pages = {750--763},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947202},
doi = {10.1109/TVLSI.2019.2947202},
timestamp = {Thu, 19 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PogueN20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20,
author = {Irith Pomeranz},
title = {Selection of Primary Output Vectors to Observe Under Multicycle Tests},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {156--162},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2941883},
doi = {10.1109/TVLSI.2019.2941883},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20a,
author = {Irith Pomeranz},
title = {Extra Clocking of {LFSR} Seeds for Improved Path Delay Fault Coverage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {544--552},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2947340},
doi = {10.1109/TVLSI.2019.2947340},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20b,
author = {Irith Pomeranz},
title = {{RETRO:} Reintroducing Tests for Improved Reverse Order Fault Simulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1930--1934},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2997762},
doi = {10.1109/TVLSI.2020.2997762},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Pomeranz20c,
author = {Irith Pomeranz},
title = {Broad-Brush Compaction for Sequential Test Generation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1940--1944},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2992097},
doi = {10.1109/TVLSI.2020.2992097},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Pomeranz20c.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ProvelengiosHT20,
author = {George Provelengios and
Daniel E. Holcomb and
Russell Tessier},
title = {Power Distribution Attacks in Multitenant FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2685--2698},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3027711},
doi = {10.1109/TVLSI.2020.3027711},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ProvelengiosHT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QoutbF20,
author = {Abdelrahman G. Qoutb and
Eby G. Friedman},
title = {Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1505--1512},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2981443},
doi = {10.1109/TVLSI.2020.2981443},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QoutbF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/QureshiPK20,
author = {Muhammad Avais Qureshi and
Jungwoo Park and
Soontae Kim},
title = {{SALE:} Smartly Allocating Low-Cost Many-Bit {ECC} for Mitigating
Read and Write Errors in {STT-RAM} Caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1357--1370},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2977131},
doi = {10.1109/TVLSI.2020.2977131},
timestamp = {Tue, 16 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/QureshiPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Rabaey20,
author = {Jan M. Rabaey},
title = {Human-Centric Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {3--11},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2956529},
doi = {10.1109/TVLSI.2019.2956529},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Rabaey20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Radonjic20,
author = {Aleksandar Radonjic},
title = {Integer Codes Correcting Double Errors and Triple-Adjacent Errors
Within a Byte},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {8},
pages = {1901--1908},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2998364},
doi = {10.1109/TVLSI.2020.2998364},
timestamp = {Wed, 26 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Radonjic20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RahimipourFKHSR20,
author = {Somayeh Rahimipour and
Wameedh Nazar Flayyih and
Noor Ain Kamsani and
Shaiful Jahari Hashim and
Mircea R. Stan and
Fakhrul Zaman Rokhani},
title = {Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting
Approximate Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2210--2222},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3012626},
doi = {10.1109/TVLSI.2020.3012626},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RahimipourFKHSR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RajRK20,
author = {Niranjan Raj and
Rajeev Kumar Ranjan and
Fabian Khateb},
title = {Flux-Controlled Memristor Emulator and Its Experimental Results},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1050--1061},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2966292},
doi = {10.1109/TVLSI.2020.2966292},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RajRK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RajaB20,
author = {Immanuel Raja and
Gaurab Banerjee},
title = {A 0.75-2.5-GHz All-Digital {RF} Transmitter With Integrated Class-E
Power Amplifier for Spectrum Sharing Applications in 5G Radios},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2109--2121},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3005438},
doi = {10.1109/TVLSI.2020.3005438},
timestamp = {Mon, 20 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RajaB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RanasingheG20,
author = {Anuradha Chathuranga Ranasinghe and
Sabih H. Gerez},
title = {Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth
Multipliers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {2028--2041},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3009239},
doi = {10.1109/TVLSI.2020.3009239},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RanasingheG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RanjanRRR20,
author = {Ashish Ranjan and
Arnab Raha and
Vijay Raghunathan and
Anand Raghunathan},
title = {Approximate Memory Compression},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {980--991},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2970041},
doi = {10.1109/TVLSI.2020.2970041},
timestamp = {Thu, 20 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RanjanRRR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RathoreMS20,
author = {Mallika Rathore and
Peter A. Milder and
Emre Salman},
title = {Error Probability Models for Voltage-Scaled Multiply-Accumulate Units},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {7},
pages = {1665--1675},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2988204},
doi = {10.1109/TVLSI.2020.2988204},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RathoreMS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RayGM20,
author = {Dwaipayan Ray and
Nithin V. George and
Pramod Kumar Meher},
title = {Analysis and Design of Unified Architectures for Zero-Attraction-Based
Sparse Adaptive Filters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1321--1325},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2965018},
doi = {10.1109/TVLSI.2020.2965018},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RayGM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReddyVKD20,
author = {Karri Manikantta Reddy and
M. H. Vasantha and
Nithin Y. B. Kumar and
Devesh Dwivedi},
title = {Design of Approximate Booth Squarer for Error-Tolerant Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1230--1241},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2976131},
doi = {10.1109/TVLSI.2020.2976131},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReddyVKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReisTJNH20,
author = {Dayane Reis and
Jonathan Takeshita and
Taeho Jung and
Michael T. Niemier and
Xiaobo Sharon Hu},
title = {Computing-in-Memory for Performance and Energy-Efficient Homomorphic
Encryption},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2300--2313},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3017595},
doi = {10.1109/TVLSI.2020.3017595},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ReisTJNH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RohaniTR20,
author = {Shokat Ganjeheizadeh Rohani and
Nima Taherinejad and
David Radakovits},
title = {A Semiparallel Full-Adder in {IMPLY} Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {297--301},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2936873},
doi = {10.1109/TVLSI.2019.2936873},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RohaniTR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoshanisefatKHS20,
author = {Shervin Roshanisefat and
Hadi Mardani Kamali and
Houman Homayoun and
Avesta Sasan},
title = {SAT-Hard Cyclic Logic Obfuscation for Protecting the {IP} in the Manufacturing
Supply Chain},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {954--967},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2968552},
doi = {10.1109/TVLSI.2020.2968552},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RoshanisefatKHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RoyBD20,
author = {Avishek Sinha Roy and
Rajdeep Biswas and
Anindya Sundar Dhar},
title = {On Fast and Exact Computation of Error Metrics in Approximate {LSB}
Adders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {876--889},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2967149},
doi = {10.1109/TVLSI.2020.2967149},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RoyBD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RyuLLKPPLL20,
author = {Kyungho Ryu and
Kil{-}Hoon Lee and
Jung{-}Pil Lim and
Jinho Kim and
Han Su Pae and
Junho Park and
Hyun{-}Wook Lim and
Jae{-}Youl Lee},
title = {An Analytical Jitter Tolerance Model for DLL-Based Clock and Data
Recovery Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {11},
pages = {2257--2267},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3018794},
doi = {10.1109/TVLSI.2020.3018794},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/RyuLLKPPLL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Salehi20,
author = {Sayed Ahmad Salehi},
title = {Low-Cost Stochastic Number Generators for Stochastic Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {992--1001},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2963678},
doi = {10.1109/TVLSI.2019.2963678},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/Salehi20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SanyalBBRC20,
author = {Sourav Sanyal and
Prabal Basu and
Aatreyi Bal and
Sanghamitra Roy and
Koushik Chakraborty},
title = {Exploring Warp Criticality in Near-Threshold {GPGPU} Applications
Using a Dynamic Choke Point Analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {2},
pages = {456--466},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2943450},
doi = {10.1109/TVLSI.2019.2943450},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SanyalBBRC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarkarBG20,
author = {Ardhendu Sarkar and
Som Banerjee and
Surajeet Ghosh},
title = {An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological
Sequence Alignment},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {12},
pages = {2598--2611},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3015138},
doi = {10.1109/TVLSI.2020.3015138},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SarkarBG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SarmaKSH20,
author = {Ranendra Kumar Sarma and
Mohd. Tasleem Khan and
Rafi Ahamed Shaik and
Jinti Hazarika},
title = {A Novel Time-Shared and LUT-Less Pipelined Architecture for {LMS}
Adaptive Filter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {1},
pages = {188--197},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2935399},
doi = {10.1109/TVLSI.2019.2935399},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SarmaKSH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SenguptaR20,
author = {Anirban Sengupta and
Mahendra Rathor},
title = {Securing Hardware Accelerators for {CE} Systems Using Biometric Fingerprinting},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {9},
pages = {1979--1992},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2999514},
doi = {10.1109/TVLSI.2020.2999514},
timestamp = {Sat, 19 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SenguptaR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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