• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 1,073 matches

• 2016
• 
  Hadi Asgharimoghaddam, Nam Sung Kim:
  SpinWise: A Practical Energy-Efficient Synchronization Technique for CMPs. SIGARCH Comput. Archit. News 44(1): 1-8 (2016)
• 
  Erik H. D'Hollander:
  High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication. SIGARCH Comput. Archit. News 44(4): 74-79 (2016)
• 
  Fatemeh Eslami, Steven J. E. Wilton:
  An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. SIGARCH Comput. Archit. News 44(4): 20-25 (2016)
• 
  Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars:
  An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM. SIGARCH Comput. Archit. News 44(4): 38-43 (2016)
• 
  Oliver Knodel, Paul R. Genssler, Rainer G. Spallek:
  Migration of long-running Tasks between Reconfigurable Resources using Virtualization. SIGARCH Comput. Archit. News 44(4): 56-61 (2016)
• 
  Ryohei Kobayashi, Tomohiro Misono, Kenji Kise:
  A High-speed Verilog HDL Simulation Method using a Lightweight Translator. SIGARCH Comput. Archit. News 44(4): 26-31 (2016)
• 
  Chengzhe Li, Lai Yoong Yee, Hiroshi Maruyama, Yoshiki Yamaguchi:
  FPGA-based Volleyball Player Tracker. SIGARCH Comput. Archit. News 44(4): 80-86 (2016)
• 
  Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang:
  FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44(4): 92-97 (2016)
• 
  Susumu Mashimo, Thiem Van Chu, Kenji Kise:
  Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator. SIGARCH Comput. Archit. News 44(4): 8-13 (2016)
• 
  Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao:
  An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. SIGARCH Comput. Archit. News 44(4): 44-49 (2016)
• 
  Lena E. Olson, Mark D. Hill:
  Probabilistic Directed Writebacks for Exclusive Caches. SIGARCH Comput. Archit. News 44(1): 9-18 (2016)
• 
  Vinod Pangracious, Mulhim Al-Doori:
  Novel Three-Dimensional Embedded FPGA Technology and Achitecture. SIGARCH Comput. Archit. News 44(4): 50-55 (2016)
• 
  Cuong Pham-Quoc, Biet Nguyen, Tran Ngoc Thinh:
  FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms. SIGARCH Comput. Archit. News 44(4): 14-19 (2016)
• 
  Shohei Sassa, Kenji Kanazawa, Shaowei Cai, Moritoshi Yasunaga:
  An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. SIGARCH Comput. Archit. News 44(4): 32-37 (2016)
• 
  Jiayi Sheng, Qingqing Xiong, Chen Yang, Martin C. Herbordt:
  Collective Communication on FPGA Clusters with Static Scheduling. SIGARCH Comput. Archit. News 44(4): 2-7 (2016)
• 
  Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung:
  Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News 44(4): 68-73 (2016)
• 
  Jubee Tada, Maiki Hosokawa, Ryusuke Egawa, Hiroaki Kobayashi:
  Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units. SIGARCH Comput. Archit. News 44(4): 62-67 (2016)
• 
  Mark Thorson:
  Internet Nuggets. SIGARCH Comput. Archit. News 44(1): 19-22 (2016)
• 
  Xusheng Zhan, Yungang Bao, Christian Bienia, Kai Li:
  PARSEC3.0: A Multicore Benchmark Suite with Network Stacks and SPLASH-2X. SIGARCH Comput. Archit. News 44(5): 1-16 (2016)
• 
  Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
  A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44(4): 86-91 (2016)
• 2015
• 
  Ahmed Al-Wattar, Shawki Areibi, Gary William Grewal:
  Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework. SIGARCH Comput. Archit. News 43(4): 46-51 (2015)
• 
  David de la Chevallerie, Jens Korinth, Andreas Koch:
  ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. SIGARCH Comput. Archit. News 43(4): 34-39 (2015)
• 
  Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati:
  10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. SIGARCH Comput. Archit. News 43(2): 2-9 (2015)
• 
  Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk:
  Parallel Genetic Algorithms on Multiple FPGAs. SIGARCH Comput. Archit. News 43(4): 86-93 (2015)
• 
  Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani:
  A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface. SIGARCH Comput. Archit. News 43(4): 22-27 (2015)
• 
  Soukaina N. Hmid, José Gabriel F. Coutinho, Wayne Luk:
  A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution. SIGARCH Comput. Archit. News 43(4): 40-45 (2015)
• 
  Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell:
  Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News 43(4): 28-33 (2015)
• 
  Ahmad Lashgar, Ebad Salehi, Amirali Baniasadi:
  A Case Study in Reverse Engineering GPGPUs: Outstanding Memory Handling Resources. SIGARCH Comput. Archit. News 43(4): 15-21 (2015)
• 
  Michael Mefenza, Nicolas Edwards, Christophe Bobda:
  Interface Based Memory Synthesis of Image Processing Applications in FPGA. SIGARCH Comput. Archit. News 43(4): 64-69 (2015)
• 
  Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano:
  Breadth First Search on Cost-efficient Multi-GPU Systems. SIGARCH Comput. Archit. News 43(4): 58-63 (2015)

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