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"A High-speed Verilog HDL Simulation Method using a Lightweight Translator."

Ryohei Kobayashi, Tomohiro Misono, Kenji Kise (2016)

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DOI: 10.1145/3039902.3039908

access: closed

type: Journal Article

metadata version: 2023-03-21

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  - journals/sigarch/KobayashiMK16
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  - https://dblp.org/rec/journals/sigarch/KobayashiMK16
Ryohei Kobayashi, Tomohiro Misono, Kenji Kise:
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. SIGARCH Comput. Archit. News 44(4): 26-31 (2016)

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