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Tung Thanh Hoang

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2020 – today

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2022
[c12]
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  - conf/irps/MaHHDMGAL22
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Wen Ma, Tung Thanh Hoang, Brian Hoskins, Matthew W. Daniels, Jabez J. McClelland, Yutong Gao, Gina C. Adam, Martin Lueker-Boden:
Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training. IRPS 2022: 35-1
2020
[c11]
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  - conf/iscas/ChoiCMHHLB20
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Won Ho Choi, Pi-Feng Chiu, Wen Ma, Gertjan Hemink, Tung Thanh Hoang, Martin Lueker-Boden, Zvonimir Bandic:
An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array. ISCAS 2020: 1-5

2010 – 2019

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2016
[c10]
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Tung Thanh Hoang, Amirali Shambayati, Andrew A. Chien:
A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems. DATE 2016: 1489-1492
2015
[j2]
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Andrew A. Chien, Tung Thanh Hoang, Dilip P. Vasudevan, Yuanwei Fang, Amirali Shambayati:
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. SIGARCH Comput. Archit. News 43(2): 2-9 (2015)
[c9]
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Tung Thanh Hoang, Amirali Shambayati, Henry Hoffmann, Andrew A. Chien:
Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators. ASAP 2015: 66-67
[c8]
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Yuanwei Fang, Tung Thanh Hoang, Michela Becchi, Andrew A. Chien:
Fast support for unstructured data processing: the unified automata processor. MICRO 2015: 533-545
2014
[c7]
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Tung Thanh Hoang, Amirali Shambayati, Calvin Deutschbein, Henry Hoffmann, Andrew A. Chien:
Performance and energy limits of a processor-integrated FFT accelerator. HPEC 2014: 1-6
2012
[c6]
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  - conf/asap/AzharSAVHAL12
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Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors:
Viterbi Accelerator for Embedded Processor Datapaths. ASAP 2012: 133-140
[c5]
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Tung Thanh Hoang, Per Larsson-Edefors:
Data-Width-Driven Power Gating of Integer Arithmetic Circuits. ISVLSI 2012: 237-242
2010
[j1]
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Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3073-3081 (2010)
[c4]
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Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors:
Design space exploration for an embedded processor with flexible datapath interconnect. ASAP 2010: 55-62
[c3]
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Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors:
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. DSD 2010: 675-680

2000 – 2009

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2009
[c2]
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Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS 2009: 1-7
[c1]
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Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC 2009: 119-122

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