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2020 – today
- 2021
[j5]Weiyun Jiang
, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang:
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1864-1873 (2021)- 2020
- [i1]Weiyun Jiang, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang:
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform. CoRR abs/2010.10638 (2020)
2010 – 2019
- 2016
- [j4]Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang:
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44(4): 92-97 (2016) - [j3]Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen, Xin-Gang Wang, Zhenhong Guo:
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(8): 1297-1308 (2016) - 2015
- [c13]Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8 - 2014
- [c12]Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang:
A survey of open source processors for FPGAs. FPL 2014: 1-6 - [c11]Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang:
Exploring architecture parameters for dual-output LUT based FPGAs. FPL 2014: 1-6 - [c10]Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin:
A semi-supervised modeling approach for performance characterization of FPGA architectures. FPL 2014: 1-6 - [c9]Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang:
Size aware placement for island style FPGAs. FPT 2014: 28-35 - 2013
- [j2]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Design space exploration for sparse matrix-matrix multiplication on FPGAs. Int. J. Circuit Theory Appl. 41(2): 205-219 (2013) - [c8]Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So:
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. FCCM 2013: 228 - [c7]Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang:
Timing-constrained minimum area/power FPGA memory mapping. FPL 2013: 1-4 - 2012
- [j1]Colin Yu Lin, Hayden Kwok-Hay So:
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. SIGARCH Comput. Archit. News 40(5): 58-63 (2012) - [c6]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). FPGA 2012: 270 - 2011
- [c5]Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong:
A Model for Peak Matrix Performance on FPGAs. FCCM 2011: 251 - [c4]Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong:
A Model for Matrix Multiplication Performance on FPGAs. FPL 2011: 305-310 - 2010
- [c3]Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So:
Design space exploration for sparse matrix-matrix multiplication on FPGAs. FPT 2010: 369-372
2000 – 2009
- 2009
- [c2]Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So:
Operation scheduling for FPGA-based reconfigurable computers. FPL 2009: 481-484 - 2008
- [c1]Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan:
A Network Based Functional Verification Method of IEEE 1394a PHY Core. ISVLSI 2008: 245-250
Coauthor Index
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