"A technology mapper for depth-constrained FPGA logic cells."

Zhenghong Jiang et al. (2015)

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DOI: 10.1109/FPL.2015.7294014

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - https://dblp.org/rec/conf/fpl/JiangZLNHYYI15
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne:
A technology mapper for depth-constrained FPGA logic cells. FPL 2015: 1-8

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