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2020 – today
- 2024
[c12]Dipjyoti Das, Lance Fernandes, Prasanna Venkatesan Ravindran, Taeyoung Song
, Chinsung Park, Nashrah Afroze, Mengkun Tian, Hang Chen, Winston Chem, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Islam Khan:
Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation. IMW 2024: 1-4- [c11]Daewon Ha, Y. Lee, S. Yoo, W. Lee, M. H. Cho, K. Yoo, S. M. Lee, S. Lee, M. Terai, T. H. Lee, J. H. Bae, K. J. Moon, C. Sung, M. Hong, D. G. Cho, K. Lee, S. W. Park, K. Park, Bong Jin Kuh, S. Hyun, Sujin Ahn, J. H. Song:
Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node. IMW 2024: 1-4 - [c10]Taeyoung Kim, Suhwan Lim, Ilho Myeong, Sanghyun Park, Suseong Noh, Seung Min Lee, Jongho Woo, Hanseung Ko, Youngji Noh, Moonkang Choi, Kiheun Lee, Sangwoo Han, Jongyeon Baek, Kijoon Kim, Dongjin Jung, Jisung Kim, Jaewoo Park, Seunghyun Kim, Hyoseok Kim, Sijung Yoo, Hyun Jae Lee, Duk-Hyun Choe, Seung-Geol Nam, Ilyoung Yoon, Chaeho Kim, Kwanzsoo Kim, Kwanzmin Park, Bong Jin Kuh, Jinseong Heo, Wanki Kim, Daewon Ha, Jaihyuk Song:
Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET. IRPS 2024: 6 - [c9]Ilho Myeong, Suhwan Lim, Taeyoung Kim, Sanghyun Park, Suseong Noh, Seung Min Lee, Jongho Woo, Hanseung Ko, Youngji Noh, Munkang Choi, Kiheun Lee, Sangwoo Han, Jongyeon Baek, Kijoon Kim, Dongjin Jung, Jisung Kim, Jaewoo Park, Seunghyun Kim, Hyoseok Kim, Ilyounz Yoon, Jaeho Kim, Kwangsoo Kim, Kwangmin Park, Bong Jin Kuh, Wanki Kim, Daewon Ha, Sujin Ahn, Jaihyuk Song, Sijung Yoo, Hyun Jae Lee, Duk-Hyun Choe, Seung-Geol Nam, Jinseong Heo:
A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND. IRPS 2024: 9 - [c8]Venkateswarlu Gaddam, Junghyeon Hwang, Hunbeom Shin, Chaeheon Kim, Giuk Kim, Hyung-Jun Kim, Jooho Lee, Hyun-Cheol Kim, Bumsu Park, Suhwan Lim, Sang Yun Kim, Kwangsoo Kim, Sungho Lee, Daewon Ha, Jinho Ahn, Sanghun Jeon:
Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology. VLSI Technology and Circuits 2024: 1-2 - [c7]Giuk Kim, Hyojun Choi, Hunbeom Shin, Sangho Lee, Sangmok Lee, Yunseok Nam, Minhyun Jung, Ilho Myeong, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Jinho Ahn, Sanghun Jeon:
In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling. VLSI Technology and Circuits 2024: 1-2 - [c6]Seong Kwang Kim, Hyeongrak Lim, Jaeyong Jeong, Young-Keun Park, Jejune Park, Sungil Park, Jaehyun Park, Daewon Ha, Byung Jin Cho, Sanghyeon Kim:
Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-High Hole Mobility. VLSI Technology and Circuits 2024: 1-2 - [c5]Z. Lin, Z. Zhang, C. Niu, H. Dou, K. Xu, M. Islam, J.-Y. Lin, C. Sung, M. Hong, Daewon Ha, H. Wang, M. A. Alam, P. D. Ye:
Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal Gate Towards Vertical Logic and Memory. VLSI Technology and Circuits 2024: 1-2 - [c4]Jaehyun Park, Juhun Park, Kyuman Hwang, Jinchan Yun, Dahye Kim, Sungil Park, Jejune Park, Jinwook Yang, Jae Won Jeong, Chuljin Yun, Jinho Bae, Sam Park, Daihong Huh, Sanghyeon Kim, Seungeun Baek, Suk Yang, Inhae Zoh, Junghan Lee, Tae-sun Kim, Younsu Ha, Sun-Jung Lee, Sang Wuk Park, Bong Jin Kuh, Daewon Ha, Sangjin Hyun, Sujin Ahn, Jaihyuk Song:
Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch. VLSI Technology and Circuits 2024: 1-2 - [i1]Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni:
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. CoRR abs/2403.04981 (2024) - 2023
- [c3]Suhwan Lim, Samki Kim, Changhee Lee, Hyeongwon Choi, Nambin Kim, Jaehun Jung, Hanvit Yang, Tae-Hun Kim, Junhee Lim, Daewon Ha, Sunghoi Hur, Jae-hoon Jang, Yu-Gyun Shin, Jaihyuk Song:
Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND. IMW 2023: 1-4 - 2022
- [c2]Daewon Ha, Hyoung-Sub Kim:
Prospective Innovation of DRAM, Flash, and Logic Technologies for Digital Transformation (DX) Era. VLSI Technology and Circuits 2022: 417-418
2010 – 2019
- 2017
- [c1]Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi:
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. ISSCC 2017: 208-209
2000 – 2009
- 2003
- [j1]Leland Chang, Yang-Kyu Choi, Daewon Ha, Pushkar Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Hu, Tsu-Jae King:
Extremely scaled silicon nano-CMOS devices. Proc. IEEE 91(11): 1860-1873 (2003)
Coauthor Index
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