• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 65 matches

• 2015
• 
  Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee:
  A fully on-chip 25MHz PVT-compensation CMOS Relaxation Oscillator. VLSI-SoC 2015: 241-245
• 
  Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler:
  Reversible circuit rewriting with simulated annealing. VLSI-SoC 2015: 286-291
• 
  Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
  Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC 2015: 110-115
• 
  Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury:
  A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends. VLSI-SoC 2015: 231-236
• 
  Ramin Bashizade, Hamid Sarbazi-Azad:
  Traffic-aware buffer reconfiguration in on-chip networks. VLSI-SoC 2015: 201-206
• 
  Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii, Enrico Macii, Massimo Poncino:
  An equation-based battery cycle life model for various battery chemistries. VLSI-SoC 2015: 57-62
• 
  Bartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sébastien Thuries, Olivier Billoint, Fabien Clermidy:
  Compact interconnect approach for networks of neural cliques using 3D technology. VLSI-SoC 2015: 116-121
• 
  Lilian Bossuet, Viktor Fischer, Pierre Bayon:
  Contactless transmission of intellectual property data to protect FPGA designs. VLSI-SoC 2015: 19-24
• 
  Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez:
  Circuit performance optimization for local intra-die process variations using a gate selection metric. VLSI-SoC 2015: 165-170
• 
  Naehyuck Chang, Kiyoung Choi:
  Message from the general chairs. VLSI-SoC 2015: VIII
• 
  Ying-Jung Chen, Shanq-Jang Ruan:
  A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVs. VLSI-SoC 2015: 349-354
• 
  Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita:
  Trace signal selection methods for post silicon debugging. VLSI-SoC 2015: 258-263
• 
  Alessandro Danese, Francesca Filini, Graziano Pravadelli:
  A time-window based approach for dynamic assertions mining on control signals. VLSI-SoC 2015: 246-251
• 
  Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
  An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC 2015: 1-6
• 
  Masahiro Fujita:
  Analysis and testing on delays with two time frames. VLSI-SoC 2015: 13-18
• 
  Michael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta:
  Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores. VLSI-SoC 2015: 25-30
• 
  Amir Masoud Gharehbaghi, Masahiro Fujita:
  Efficient signature-based sub-circuit matching. VLSI-SoC 2015: 280-285
• 
  Tara Ghasempouri, Graziano Pravadelli:
  On the estimation of assertion interestingness. VLSI-SoC 2015: 325-330
• 
  Andres F. Gomez, Víctor H. Champac:
  A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging. VLSI-SoC 2015: 297-302
• 
  Jun Guo, Peng Liu, Weidong Wang:
  Physical-based modeling and fast simulation of wireline links. VLSI-SoC 2015: 252-257
• 
  Yuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra:
  Trace Buffer Attack: Security versus observability study in post-silicon debug. VLSI-SoC 2015: 355-360
• 
  Xabier Iturbe, Didier Keymeulen, Emre Ozer, Patrick Yiu, Daniel Berisford, Kevin P. Hand, Robert Carlson:
  An integrated SoC for science data processing in next-generation space flight instruments avionics. VLSI-SoC 2015: 134-141
• 
  Manish Kumar Jaiswal, Hayden Kwok-Hay So:
  Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC 2015: 213-218
• 
  Mini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Tae-Hyoung Kim:
  Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing. VLSI-SoC 2015: 159-164
• 
  John Jose, Joe Augustine, Sijin Sebastian:
  Dynamic migratory selection strategy for adaptive routing in mesh NoCs. VLSI-SoC 2015: 343-348
• 
  Asim Khan, Muhammad Umar Karim Khan, Muhammad Bilal, Chong-Min Kyung:
  Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local features. VLSI-SoC 2015: 142-148
• 
  Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet:
  A generic clock controller for low power systems: Experimentation on an AXI bus. VLSI-SoC 2015: 307-312
• 
  Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi:
  Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. VLSI-SoC 2015: 183-188
• 
  Gain Kim, Raffaele Capoccia, Yusuf Leblebici:
  Design optimization of polyphase digital down converters for extremely high frequency wireless communications. VLSI-SoC 2015: 207-212
• 
  Matthew M. Kim, Karl M. Fant, Paul Beckett:
  Design of asynchronous RISC CPU register-file Write-Back queue. VLSI-SoC 2015: 31-36

skipping 35 more matches