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2020 – today
- 2023
[c5]Mingi Yoo, Jaeyong Song
, Jounghoo Lee, Namhyung Kim, Youngsok Kim, Jinho Lee:
SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Accelerators. HPCA 2023: 1-14- [i2]Mingi Yoo, Jaeyong Song, Hyeyoon Lee, Jounghoo Lee, Namhyung Kim, Youngsok Kim, Jinho Lee:
Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators. CoRR abs/2301.09813 (2023) - [i1]Mingi Yoo, Jaeyong Song, Jounghoo Lee, Namhyung Kim, Youngsok Kim, Jinho Lee:
SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Accelerators. CoRR abs/2301.10388 (2023) - 2022
- [j5]Namhyung Kim, Hanmin Park, Dongwoo Lee, Sungbum Kang, Jinho Lee, Kiyoung Choi:
ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator. IEEE Trans. Computers 71(7): 1537-1550 (2022) - [c4]Mingi Yoo, Jaeyong Song, Hyeyoon Lee, Jounghoo Lee, Namhyung Kim, Youngsok Kim, Jinho Lee:
Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators. PACT 2022: 40-53 - 2021
- [j4]Mingi Yoo, Jaeyong Song, Jounghoo Lee, Namhyung Kim, Youngsok Kim, Jinho Lee:
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing. IEEE Comput. Archit. Lett. 20(2): 102-105 (2021) - 2020
- [c3]Changmin Lee, Wonjae Shin, Dae Jeong Kim, Yongjun Yu, Sung-Joon Kim, Taekyeong Ko, Deokho Seo, Jongmin Park, Kwanghee Lee, Seongho Choi, Namhyung Kim, Vishak G, Arun George, Vishwas V, Donghun Lee, Kang-Woo Choi, Changbin Song, Dohan Kim, Insu Choi, Ilgyu Jung, Yong Ho Song, Jinman Han:
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces. HPCA 2020: 502-514
2010 – 2019
- 2019
- [c2]Gunhee Lee, Hanmin Park, Namhyung Kim, Joonsang Yu, Sujeong Jo, Kiyoung Choi:
Acceleration of DNN Backward Propagation by Selective Computation of Gradients. DAC 2019: 85 - 2018
- [j3]Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sánchez, Donghoon Yoo, Soojung Ryu:
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. ACM Trans. Archit. Code Optim. 15(1): 10:1-10:23 (2018) - 2016
- [j2]Namhyung Kim, Kiyoung Choi:
Exploration of trade-offs in the design of volatile STT-RAM cache. J. Syst. Archit. 71: 23-31 (2016) - 2015
- [c1]Namhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi:
Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM. VLSI-SoC 2015: 183-188 - 2014
- [j1]Namhyung Kim, Kyungmin Kim, Jae-Sung Rieh:
A Triple-Push Voltage Controlled Oscillator in 0.13-µm RFCMOS Technology Operating Near 177GHz. IEICE Trans. Electron. 97-C(5): 444-447 (2014)
Coauthor Index
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