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Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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@inproceedings{DBLP:conf/vlsi/AbbasizadehRL15,
  author       = {Hamed Abbasizadeh and
                  Behnam Samadpoor Rikan and
                  Kang{-}Yoon Lee},
  title        = {A fully on-chip 25MHz PVT-compensation {CMOS} Relaxation Oscillator},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {241--245},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314423},
  doi          = {10.1109/VLSI-SOC.2015.7314423},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/AbbasizadehRL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/AbdessaiedSDD15,
  author       = {Nabila Abdessaied and
                  Mathias Soeken and
                  Gerhard W. Dueck and
                  Rolf Drechsler},
  title        = {Reversible circuit rewriting with simulated annealing},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {286--291},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314431},
  doi          = {10.1109/VLSI-SOC.2015.7314431},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/AbdessaiedSDD15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/AmagasakiTZIKS15,
  author       = {Motoki Amagasaki and
                  Yuto Takeuchi and
                  Qian Zhao and
                  Masahiro Iida and
                  Morihiro Kuga and
                  Toshinori Sueyoshi},
  title        = {Architecture exploration of 3D {FPGA} to minimize internal layer connection},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {110--115},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314401},
  doi          = {10.1109/VLSI-SOC.2015.7314401},
  timestamp    = {Wed, 18 Oct 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/AmagasakiTZIKS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/AmaravatiCR15,
  author       = {Anvesha Amaravati and
                  Manan Chugh and
                  Arijit Raychowdhury},
  title        = {A time interleaved {DAC} sharing {SAR} Pipeline {ADC} for ultra-low
                  power camera front ends},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {231--236},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314421},
  doi          = {10.1109/VLSI-SOC.2015.7314421},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/AmaravatiCR15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/BashizadeS15,
  author       = {Ramin Bashizade and
                  Hamid Sarbazi{-}Azad},
  title        = {Traffic-aware buffer reconfiguration in on-chip networks},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {201--206},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314416},
  doi          = {10.1109/VLSI-SOC.2015.7314416},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/BashizadeS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/BoccaSSMMP15,
  author       = {Alberto Bocca and
                  Alessandro Sassone and
                  Donghwa Shin and
                  Alberto Macii and
                  Enrico Macii and
                  Massimo Poncino},
  title        = {An equation-based battery cycle life model for various battery chemistries},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {57--62},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314392},
  doi          = {10.1109/VLSI-SOC.2015.7314392},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/BoccaSSMMP15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/BoguslawskiSHST15,
  author       = {Bartosz Boguslawski and
                  Hossam Sarhan and
                  Fr{\'{e}}d{\'{e}}ric Heitzmann and
                  Fabrice Seguin and
                  S{\'{e}}bastien Thuries and
                  Olivier Billoint and
                  Fabien Clermidy},
  title        = {Compact interconnect approach for networks of neural cliques using
                  3D technology},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {116--121},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314402},
  doi          = {10.1109/VLSI-SOC.2015.7314402},
  timestamp    = {Wed, 12 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/BoguslawskiSHST15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/BossuetFB15,
  author       = {Lilian Bossuet and
                  Viktor Fischer and
                  Pierre Bayon},
  title        = {Contactless transmission of intellectual property data to protect
                  {FPGA} designs},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {19--24},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314385},
  doi          = {10.1109/VLSI-SOC.2015.7314385},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/BossuetFB15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ChampacRG15,
  author       = {V{\'{\i}}ctor H. Champac and
                  Alejandra Nicte{-}ha Reyes and
                  Andres F. Gomez},
  title        = {Circuit performance optimization for local intra-die process variations
                  using a gate selection metric},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {165--170},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314410},
  doi          = {10.1109/VLSI-SOC.2015.7314410},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ChampacRG15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ChangC15,
  author       = {Naehyuck Chang and
                  Kiyoung Choi},
  title        = {Message from the general chairs},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {VIII},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314376},
  doi          = {10.1109/VLSI-SOC.2015.7314376},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ChangC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ChenR15,
  author       = {Ying{-}Jung Chen and
                  Shanq{-}Jang Ruan},
  title        = {A cluster-based reliability- and thermal-aware 3D floorplanning using
                  redundant STSVs},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {349--354},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314442},
  doi          = {10.1109/VLSI-SOC.2015.7314442},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ChenR15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ChoudharyGMF15,
  author       = {Shridhar Choudhary and
                  Amir Masoud Gharehbaghi and
                  Takeshi Matsumoto and
                  Masahiro Fujita},
  title        = {Trace signal selection methods for post silicon debugging},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {258--263},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314426},
  doi          = {10.1109/VLSI-SOC.2015.7314426},
  timestamp    = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ChoudharyGMF15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/DaneseFP15,
  author       = {Alessandro Danese and
                  Francesca Filini and
                  Graziano Pravadelli},
  title        = {A time-window based approach for dynamic assertions mining on control
                  signals},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {246--251},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314424},
  doi          = {10.1109/VLSI-SOC.2015.7314424},
  timestamp    = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/DaneseFP15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/FlachMFPBJR15,
  author       = {Guilherme Flach and
                  Jucemar Monteiro and
                  Mateus Foga{\c{c}}a and
                  Julia Casarin Puget and
                  Paulo F. Butzen and
                  Marcelo O. Johann and
                  Ricardo Augusto da Luz Reis},
  title        = {An Incremental Timing-Driven flow using quadratic formulation for
                  detailed placement},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314382},
  doi          = {10.1109/VLSI-SOC.2015.7314382},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/FlachMFPBJR15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/Fujita15,
  author       = {Masahiro Fujita},
  title        = {Analysis and testing on delays with two time frames},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {13--18},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314384},
  doi          = {10.1109/VLSI-SOC.2015.7314384},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/Fujita15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/GautschiTPBSFBA15,
  author       = {Michael Gautschi and
                  Andreas Traber and
                  Antonio Pullini and
                  Luca Benini and
                  Michele Scandale and
                  Alessandro Di Federico and
                  Michele Beretta and
                  Giovanni Agosta},
  title        = {Tailoring instruction-set extensions for an ultra-low power tightly-coupled
                  cluster of OpenRISC cores},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {25--30},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314386},
  doi          = {10.1109/VLSI-SOC.2015.7314386},
  timestamp    = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/GautschiTPBSFBA15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/GharehbaghiF15,
  author       = {Amir Masoud Gharehbaghi and
                  Masahiro Fujita},
  title        = {Efficient signature-based sub-circuit matching},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {280--285},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314430},
  doi          = {10.1109/VLSI-SOC.2015.7314430},
  timestamp    = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/GharehbaghiF15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/GhasempouriP15,
  author       = {Tara Ghasempouri and
                  Graziano Pravadelli},
  title        = {On the estimation of assertion interestingness},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {325--330},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314438},
  doi          = {10.1109/VLSI-SOC.2015.7314438},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/GhasempouriP15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/GomezC15,
  author       = {Andres F. Gomez and
                  V{\'{\i}}ctor H. Champac},
  title        = {A new sizing approach for lifetime improvement of nanoscale digital
                  circuits due to {BTI} aging},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {297--302},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314433},
  doi          = {10.1109/VLSI-SOC.2015.7314433},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/GomezC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/Guo0W15,
  author       = {Jun Guo and
                  Peng Liu and
                  Weidong Wang},
  title        = {Physical-based modeling and fast simulation of wireline links},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {252--257},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314425},
  doi          = {10.1109/VLSI-SOC.2015.7314425},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/Guo0W15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/HuangCM15,
  author       = {Yuanwen Huang and
                  Anupam Chattopadhyay and
                  Prabhat Mishra},
  title        = {Trace Buffer Attack: Security versus observability study in post-silicon
                  debug},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {355--360},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314443},
  doi          = {10.1109/VLSI-SOC.2015.7314443},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/HuangCM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/IturbeKOYBHC15,
  author       = {Xabier Iturbe and
                  Didier Keymeulen and
                  Emre Ozer and
                  Patrick Yiu and
                  Daniel Berisford and
                  Kevin P. Hand and
                  Robert Carlson},
  title        = {An integrated SoC for science data processing in next-generation space
                  flight instruments avionics},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {134--141},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314405},
  doi          = {10.1109/VLSI-SOC.2015.7314405},
  timestamp    = {Wed, 11 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/IturbeKOYBHC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/JaiswalS15,
  author       = {Manish Kumar Jaiswal and
                  Hayden Kwok{-}Hay So},
  title        = {Dual-mode double precision / two-parallel single precision floating
                  point multiplier architecture},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {213--218},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314418},
  doi          = {10.1109/VLSI-SOC.2015.7314418},
  timestamp    = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/JaiswalS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/JayakrishnanCGH15,
  author       = {Mini Jayakrishnan and
                  Alan Chang and
                  Jos{\'{e}} Pineda de Gyvez and
                  Tae{-}Hyoung Kim},
  title        = {Slack-aware timing margin redistribution technique utilizing error
                  avoidance flip-flops and time borrowing},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {159--164},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314409},
  doi          = {10.1109/VLSI-SOC.2015.7314409},
  timestamp    = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/JayakrishnanCGH15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/JoseAS15,
  author       = {John Jose and
                  Joe Augustine and
                  Sijin Sebastian},
  title        = {Dynamic migratory selection strategy for adaptive routing in mesh
                  NoCs},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {343--348},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314441},
  doi          = {10.1109/VLSI-SOC.2015.7314441},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/JoseAS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/KhanKBK15,
  author       = {Asim Khan and
                  Muhammad Umar Karim Khan and
                  Muhammad Bilal and
                  Chong{-}Min Kyung},
  title        = {Hardware architecture and optimization of sliding window based pedestrian
                  detection on {FPGA} for high resolution images by varying local features},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {142--148},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314406},
  doi          = {10.1109/VLSI-SOC.2015.7314406},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/KhanKBK15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/KhatibACASF15,
  author       = {Chadi Al Khatib and
                  Claire Aupetit and
                  Cyril Chevalier and
                  Chouki Aktouf and
                  Gilles Sicard and
                  Laurent Fesquet},
  title        = {A generic clock controller for low power systems: Experimentation
                  on an {AXI} bus},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {307--312},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314435},
  doi          = {10.1109/VLSI-SOC.2015.7314435},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/KhatibACASF15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/KimASC15,
  author       = {Namhyung Kim and
                  Junwhan Ahn and
                  Woong Seo and
                  Kiyoung Choi},
  title        = {Energy-efficient exclusive last-level hybrid caches consisting of
                  {SRAM} and {STT-RAM}},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {183--188},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314413},
  doi          = {10.1109/VLSI-SOC.2015.7314413},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/KimASC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/KimCL15,
  author       = {Gain Kim and
                  Raffaele Capoccia and
                  Yusuf Leblebici},
  title        = {Design optimization of polyphase digital down converters for extremely
                  high frequency wireless communications},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {207--212},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314417},
  doi          = {10.1109/VLSI-SOC.2015.7314417},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/KimCL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/KimFB15,
  author       = {Matthew M. Kim and
                  Karl M. Fant and
                  Paul Beckett},
  title        = {Design of asynchronous {RISC} {CPU} register-file Write-Back queue},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {31--36},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314387},
  doi          = {10.1109/VLSI-SOC.2015.7314387},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/KimFB15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/KimKKPC15,
  author       = {S. E. Kim and
                  T. W. Kang and
                  S. W. Kang and
                  K. H. Park and
                  M. A. Chung},
  title        = {High-efficiency voltage regulation stage in energy harvesting systems},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {237--240},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314422},
  doi          = {10.1109/VLSI-SOC.2015.7314422},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/KimKKPC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/LeeKBE15,
  author       = {Jae{-}Jin Lee and
                  Chan Kim and
                  Kyungjin Byun and
                  Nak{-}Woong Eum},
  title        = {Virtual prototype based on Aldebarn {CPU} core},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {303--306},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314434},
  doi          = {10.1109/VLSI-SOC.2015.7314434},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/LeeKBE15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/LeeKKK15,
  author       = {Jaemin Lee and
                  Seungwon Kim and
                  Youngmin Kim and
                  Seokhyeong Kang},
  title        = {An optimal operating point by using error monitoring circuits with
                  an error-resilient technique},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {69--73},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314394},
  doi          = {10.1109/VLSI-SOC.2015.7314394},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/LeeKKK15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/LiLWYYYL15,
  author       = {Zheng Li and
                  Chenchen Liu and
                  Yandan Wang and
                  Bonan Yan and
                  Chaofei Yang and
                  Jianlei Yang and
                  Hai Li},
  title        = {An overview on memristor crossabr based neuromorphic circuit and architecture},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {52--56},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314391},
  doi          = {10.1109/VLSI-SOC.2015.7314391},
  timestamp    = {Sun, 05 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/LiLWYYYL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/LiouHCC15,
  author       = {Jing{-}Jia Liou and
                  Meng{-}Ta Hsieh and
                  Jun{-}Fei Cherng and
                  Harry H. Chen},
  title        = {Cost reduction of system-level tests with stressed structural tests
                  and {SVM}},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {177--182},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314412},
  doi          = {10.1109/VLSI-SOC.2015.7314412},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/LiouHCC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/LowSZ15,
  author       = {Qiong Wei Low and
                  Liter Siek and
                  Mi Zhou},
  title        = {A high efficiency rectifier for inductively power transfer application},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {270--273},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314428},
  doi          = {10.1109/VLSI-SOC.2015.7314428},
  timestamp    = {Fri, 30 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/LowSZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/MackoJC15,
  author       = {Dominik Macko and
                  Katar{\'{\i}}na Jelemensk{\'{a}} and
                  Pavel Cic{\'{a}}k},
  title        = {Power-management high-level synthesis},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {63--68},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314393},
  doi          = {10.1109/VLSI-SOC.2015.7314393},
  timestamp    = {Tue, 13 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/MackoJC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/MuzaffarE15,
  author       = {Shahzad Muzaffar and
                  Ibrahim M. Elfadel},
  title        = {Timing and robustness analysis of Pulsed-Index protocols for single-channel
                  IoT communications},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {225--230},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314420},
  doi          = {10.1109/VLSI-SOC.2015.7314420},
  timestamp    = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/MuzaffarE15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/Nicolas-Nicolaz15,
  author       = {Pierre Nicolas{-}Nicolaz and
                  Kiyoung Choi},
  title        = {Dynamic error tracking and supply voltage adjustment for low power},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {74--79},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314395},
  doi          = {10.1109/VLSI-SOC.2015.7314395},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/Nicolas-Nicolaz15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/PandiyanM15,
  author       = {Manikandan Pandiyan and
                  Geetha Mani},
  title        = {Embedded low power analog {CMOS} Fuzzy Logic Controller chip for industrial
                  applications},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {43--48},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314389},
  doi          = {10.1109/VLSI-SOC.2015.7314389},
  timestamp    = {Mon, 05 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/PandiyanM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/PandiyanMJS15,
  author       = {Manikandan Pandiyan and
                  Geetha Mani and
                  Jovitha Jerome and
                  Natarajan S.},
  title        = {Integrating wearable low power {CMOS} {ECG} acquisition SoC with decision
                  making system for {WSBN} applications},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {154--158},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314408},
  doi          = {10.1109/VLSI-SOC.2015.7314408},
  timestamp    = {Tue, 19 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/PandiyanMJS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ParkAPY15,
  author       = {Hyunsun Park and
                  Junwhan Ahn and
                  Eunhyeok Park and
                  Sungjoo Yoo},
  title        = {Locality-aware vertex scheduling for GPU-based graph computation},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {195--200},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314415},
  doi          = {10.1109/VLSI-SOC.2015.7314415},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkAPY15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ParkBE15,
  author       = {Seongmo Park and
                  Kyungjin Byun and
                  Nak{-}Woong Eum},
  title        = {A hybrid embedded compression codec engine for ultra {HD} video application},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {292--296},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314432},
  doi          = {10.1109/VLSI-SOC.2015.7314432},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkBE15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ParkKYP15,
  author       = {Hyunsun Park and
                  Chanha Kim and
                  Sungjoo Yoo and
                  Chanik Park},
  title        = {Filtering dirty data in {DRAM} to reduce {PRAM} writes},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {319--324},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314437},
  doi          = {10.1109/VLSI-SOC.2015.7314437},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkKYP15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ParkLKK15,
  author       = {Hyungil Park and
                  Ingi Lim and
                  Sungweon Kang and
                  Whan{-}woo Kim},
  title        = {10Mbps human body communication SoC for {BAN}},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {149--153},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314407},
  doi          = {10.1109/VLSI-SOC.2015.7314407},
  timestamp    = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkLKK15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ParkSL15,
  author       = {Jaehyun Park and
                  Donghwa Shin and
                  Hyung Gyu Lee},
  title        = {Prefetch-based dynamic row buffer management for {LPDDR2-NVM} devices},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {98--103},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314399},
  doi          = {10.1109/VLSI-SOC.2015.7314399},
  timestamp    = {Mon, 19 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkSL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ParkSL15a,
  author       = {Jaehyun Park and
                  Donghwa Shin and
                  Hyung Gyu Lee},
  title        = {Design space exploration of row buffer architecture for phase change
                  memory with {LPDDR2-NVM} interface},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {104--109},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314400},
  doi          = {10.1109/VLSI-SOC.2015.7314400},
  timestamp    = {Mon, 19 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/ParkSL15a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/Parthasarathy15,
  author       = {Ananthanarayanan Parthasarathy},
  title        = {Design and analysis of search algorithms for lower power consumption
                  and faster convergence of {DAC} input of {SAR-ADC} in 65nm {CMOS}},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {274--279},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314429},
  doi          = {10.1109/VLSI-SOC.2015.7314429},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/Parthasarathy15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/PaulBS15,
  author       = {Sudipta Paul and
                  Pritha Banerjee and
                  Susmita Sur{-}Kolay},
  title        = {Flare reduction in {EUV} Lithography by perturbation of wire segments},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {7--12},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314383},
  doi          = {10.1109/VLSI-SOC.2015.7314383},
  timestamp    = {Sat, 02 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/PaulBS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/QuiringOB15,
  author       = {Artur Quiring and
                  Markus Olbrich and
                  Erich Barke},
  title        = {Fast global interconnnect driven 3D floorplanning},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {313--318},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314436},
  doi          = {10.1109/VLSI-SOC.2015.7314436},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/QuiringOB15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/RakossySALC15,
  author       = {Zolt{\'{a}}n Endre R{\'{a}}kossy and
                  Dominik Stengele and
                  Gerd Ascheid and
                  Rainer Leupers and
                  Anupam Chattopadhyay},
  title        = {Exploiting scalable {CGRA} mapping of {LU} for energy efficiency using
                  the Layers architecture},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {337--342},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314440},
  doi          = {10.1109/VLSI-SOC.2015.7314440},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/RakossySALC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/RoyMGR15,
  author       = {Surajit Kumar Roy and
                  Supriyo Mandal and
                  Chandan Giri and
                  Hafizur Rahaman},
  title        = {A thermal estimation model for 3D {IC} using liquid cooled microchannels
                  and thermal TSVs},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {122--127},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314403},
  doi          = {10.1109/VLSI-SOC.2015.7314403},
  timestamp    = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/RoyMGR15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/SaeedMAS15,
  author       = {Samah Mohamed Saeed and
                  Bodhisatwa Mazumdar and
                  Sk Subidh Ali and
                  Ozgur Sinanoglu},
  title        = {Timing attack on {NEMS} relay based design of {AES}},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {264--269},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314427},
  doi          = {10.1109/VLSI-SOC.2015.7314427},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsi/SaeedMAS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/SeoS15,
  author       = {Jae{-}sun Seo and
                  Mingoo Seok},
  title        = {Digital {CMOS} neuromorphic processor design featuring unsupervised
                  online learning},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {49--51},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314390},
  doi          = {10.1109/VLSI-SOC.2015.7314390},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/SeoS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/SeyidBL15,
  author       = {Kerem Seyid and
                  Sebastien Blanc and
                  Yusuf Leblebici},
  title        = {Hardware implementation of real-time multiple frame super-resolution},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {219--224},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314419},
  doi          = {10.1109/VLSI-SOC.2015.7314419},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/SeyidBL15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ShimS15,
  author       = {Seongbo Shim and
                  Youngsoo Shin},
  title        = {Physical design and mask optimization for directed self-assembly lithography
                  {(DSAL)}},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {80--85},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314396},
  doi          = {10.1109/VLSI-SOC.2015.7314396},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ShimS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/ShinT15,
  author       = {Youngsoo Shin and
                  Chi{-}Ying Tsui},
  title        = {Message from the technical program chairs},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {IX},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314377},
  doi          = {10.1109/VLSI-SOC.2015.7314377},
  timestamp    = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/ShinT15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/SrinivasanMB15,
  author       = {Manikantan Srinivasan and
                  C. Siva Ram Murthy and
                  Anusuya Balasubramanian},
  title        = {Modular performance analysis of Multicore SoC-based small cell {LTE}
                  base station},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {37--42},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314388},
  doi          = {10.1109/VLSI-SOC.2015.7314388},
  timestamp    = {Thu, 15 Jun 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/SrinivasanMB15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/TangHM15,
  author       = {Jia Wei Tang and
                  Yuan Wen Hau and
                  Muhammad N. Marsono},
  title        = {Hardware/software partitioning of embedded System-on-Chip applications},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {331--336},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314439},
  doi          = {10.1109/VLSI-SOC.2015.7314439},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/TangHM15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/TsaiWS15,
  author       = {Chun{-}Jen Tsai and
                  Tsung{-}Han Wu and
                  Hung{-}Cheng Su},
  title        = {{JAIP-MP:} {A} four-core Java application processor},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {189--194},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314414},
  doi          = {10.1109/VLSI-SOC.2015.7314414},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/TsaiWS15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/UbarJOR15,
  author       = {Raimund Ubar and
                  Lembit Jurimagi and
                  Elmet Orasson and
                  Jaan Raik},
  title        = {Scalable algorithm for structural fault collapsing in digital circuits},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {171--176},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314411},
  doi          = {10.1109/VLSI-SOC.2015.7314411},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/UbarJOR15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/WeiZ15,
  author       = {Lin Wei and
                  Lei Zhou},
  title        = {An equilibrium partitioning method for multicast traffic in 3D NoC
                  architecture},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {128--133},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314404},
  doi          = {10.1109/VLSI-SOC.2015.7314404},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/WeiZ15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/XueCYH15,
  author       = {Yuan Xue and
                  Patrick Cronin and
                  Chengmo Yang and
                  Jingtong Hu},
  title        = {Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate
                  reconfiguration and increase programming cycles},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {92--97},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314398},
  doi          = {10.1109/VLSI-SOC.2015.7314398},
  timestamp    = {Sat, 16 Sep 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/XueCYH15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi/YangV15,
  author       = {Chengmo Yang and
                  Maria Ruiz Varela},
  title        = {Qualifying non-volatile register files for embedded systems through
                  compiler-directed write minimization and balancing},
  booktitle    = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  pages        = {86--91},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://doi.org/10.1109/VLSI-SoC.2015.7314397},
  doi          = {10.1109/VLSI-SOC.2015.7314397},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/YangV15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/vlsi/2015soc,
  title        = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
                  VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
  publisher    = {{IEEE}},
  year         = {2015},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/7304349/proceeding},
  isbn         = {978-1-4673-9140-5},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi/2015soc.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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