• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 94 matches

• 2010
• 
  Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
  Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20
• 
  Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye:
  Clock skew reduction by self-compensating manufacturing variability with on-chip sensors. ACM Great Lakes Symposium on VLSI 2010: 197-202
• 
  Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella:
  An integrated thermal estimation framework for industrial embedded platforms. ACM Great Lakes Symposium on VLSI 2010: 293-298
• 
  Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
  A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI 2010: 39-44
• 
  Kanak Agarwal:
  On-die sensors for measuring process and environmental variations in integrated circuits. ACM Great Lakes Symposium on VLSI 2010: 147-150
• 
  Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden:
  An effective approach for large scale floorplanning. ACM Great Lakes Symposium on VLSI 2010: 107-110
• 
  Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi:
  Performance assessment of analog circuits with carbon nanotube FET (CNFET). ACM Great Lakes Symposium on VLSI 2010: 163-166
• 
  Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
  Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134
• 
  Sumanth Amarchinta, Dhireesha Kudithipudi:
  Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffers. ACM Great Lakes Symposium on VLSI 2010: 369-372
• 
  Raid Ayoub, Alex Orailoglu:
  Performance and energy efficient cache migrationapproach for thermal management in embedded systems. ACM Great Lakes Symposium on VLSI 2010: 365-368
• 
  Andrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries:
  A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. ACM Great Lakes Symposium on VLSI 2010: 311-316
• 
  Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban:
  Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304
• 
  Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
  Aging effects of leakage optimizations for caches. ACM Great Lakes Symposium on VLSI 2010: 95-98
• 
  Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez:
  Fast instruction cache modeling for approximate timed HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2010: 191-196
• 
  Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer:
  Design of embedded MRAM macros for memory-in-logic applications. ACM Great Lakes Symposium on VLSI 2010: 155-158
• 
  Hao Chen, Jie Han:
  Stochastic computational models for accurate reliability evaluation of logic circuits. ACM Great Lakes Symposium on VLSI 2010: 61-66
• 
  Yu-Chen Chen, Hou-Yu Pang, Kuen-Wey Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su:
  Via configurable three-input lookup-tables for structured ASICs. ACM Great Lakes Symposium on VLSI 2010: 49-54
• 
  Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram:
  Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI 2010: 173-178
• 
  Ilya Chukhman, Peter Petrov:
  Context-aware TLB preloading for interference reduction in embedded multi-tasked systems. ACM Great Lakes Symposium on VLSI 2010: 401-404
• 
  David Cuesta, José Luis Ayala, José Ignacio Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii:
  Thermal-aware floorplanning exploration for 3D multi-core architectures. ACM Great Lakes Symposium on VLSI 2010: 99-102
• 
  Basab Datta, Wayne P. Burleson:
  Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. ACM Great Lakes Symposium on VLSI 2010: 341-346
• 
  Basab Datta, Wayne P. Burleson:
  Circuit-level NBTI macro-models for collaborative reliability monitoring. ACM Great Lakes Symposium on VLSI 2010: 453-458
• 
  Kanupriya Gulati, Sunil P. Khatri:
  Boolean satisfiability on a graphics processor. ACM Great Lakes Symposium on VLSI 2010: 123-126
• 
  Xin He, Afshin Abdollahi:
  Cost aware fault tolerant logic synthesis in presence of soft errors. ACM Great Lakes Symposium on VLSI 2010: 151-154
• 
  Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
  Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI 2010: 9-14
• 
  Keisuke Inoue, Mineo Kaneko:
  A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. ACM Great Lakes Symposium on VLSI 2010: 111-114
• 
  Kagan Irez, Jiaping Hu, Charles A. Zukowski:
  Characteristics of MS-CMOS logic in sub-32nm technologies. ACM Great Lakes Symposium on VLSI 2010: 393-396
• 
  Renatas Jakushokas, Eby G. Friedman:
  Line width optimization for interdigitated power/ground networks. ACM Great Lakes Symposium on VLSI 2010: 329-334
• 
  Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
  Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI 2010: 281-286
• 
  Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
  Gating internal nodes to reduce power during scan shift. ACM Great Lakes Symposium on VLSI 2010: 79-84

skipping 64 more matches