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Dheepakkumaran Jayaraman

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2010 – 2019

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2013
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Dheepakkumaran Jayaraman, Spyros Tragoudas:
Performance validation through implicit removal of infeasible paths of the behavioral description. ISQED 2013: 552-557
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Dheepakkumaran Jayaraman, Spyros Tragoudas:
A method to determine the sensitization probability of a non-robustly testable path. ISQED 2013: 676-681
2011
[c3]
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Dheepakkumaran Jayaraman, Spyros Tragoudas:
Occurrence probability analysis of a path at the architectural level. ISQED 2011: 464-468
2010
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Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Scan Shift Power Reduction by Gating Internal Nodes. J. Low Power Electron. 6(2): 311-319 (2010)
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Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Gating internal nodes to reduce power during scan shift. ACM Great Lakes Symposium on VLSI 2010: 79-84

2000 – 2009

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2008
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Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas:
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. ITC 2008: 1-10

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