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ORCIDRajamani Sethuram
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2010 – 2019
- 2011
[c7]Sandesh Prabhakar, Rajamani Sethuram, Michael S. Hsiao:
Trace Buffer-Based Silicon Debug with Lossless Compression. VLSI Design 2011: 358-363- [c6]Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma:
Leakage power profiling and leakage power reduction using DFT hardware. VTS 2011: 46-51 - 2010
- [j1]Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Scan Shift Power Reduction by Gating Internal Nodes. J. Low Power Electron. 6(2): 311-319 (2010) - [c5]Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas:
Gating internal nodes to reduce power during scan shift. ACM Great Lakes Symposium on VLSI 2010: 79-84
2000 – 2009
- 2008
- [c4]Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal:
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS 2008: 329-335 - 2007
- [c3]Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell:
Zero Cost Test Point Insertion Technique for Structured ASICs. VLSI Design 2007: 357-363 - [c2]Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell:
A Neural Net Branch Predictor to Reduce Power. VLSI Design 2007: 679-684 - 2006
- [c1]Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell:
Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs. ATS 2006: 339-348
Coauthor Index
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