- Yukio Miyasaka, Akihiro Goda, Ashish Mittal, Masahiro Fujita:
Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. IPSJ Trans. Syst. LSI Des. Methodol. 13: 31-34 (2020) - Kenshu Seto:
Shift Register Initialization in Scalar Replacement for Reducing Code Size. IPSJ Trans. Syst. LSI Des. Methodol. 13: 2-9 (2020) - Kotaro Shimamura, Naohiro Ikeda:
Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator. IPSJ Trans. Syst. LSI Des. Methodol. 13: 21-30 (2020) - Atsushi Takahashi
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Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 13: 1 (2020) - Sheldon X.-D. Tan, Zeyu Sun, Sheriff Sadiqbatcha:
Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip. IPSJ Trans. Syst. LSI Des. Methodol. 13: 42-55 (2020) - Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita:
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality. IPSJ Trans. Syst. LSI Des. Methodol. 13: 35-38 (2020) - 2019
- Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 38-41 (2019) - A. K. M. Mahfuzul Islam, Hidetoshi Onodera:
Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation. IPSJ Trans. Syst. LSI Des. Methodol. 12: 2-12 (2019) - Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi:
Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ Trans. Syst. LSI Des. Methodol. 12: 78-80 (2019) - Hiroki Koyasu, Yasuhiro Takahashi:
Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 12: 50-52 (2019) - Yang Liu, Lin Meng, Hiroyuki Tomiyama:
A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 74-77 (2019) - Takafumi Miyazaki, Shunsuke Takai, Ittetsu Taniguchi, Hiroyuki Tomiyama:
An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC. IPSJ Trans. Syst. LSI Des. Methodol. 12: 46-49 (2019) - Kenshu Seto:
Scalar Replacement with Circular Buffers. IPSJ Trans. Syst. LSI Des. Methodol. 12: 13-21 (2019) - Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 65-73 (2019) - Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 12: 42-45 (2019) - Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi:
Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 12: 22-37 (2019) - Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 12: 1 (2019) - Chaofei Yang, Ximing Qiao, Yiran Chen:
Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory. IPSJ Trans. Syst. LSI Des. Methodol. 12: 53-64 (2019) - 2018
- Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler:
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11: 29-45 (2018) - Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - Kenshu Seto:
Scalar Replacement with Polyhedral Model. IPSJ Trans. Syst. LSI Des. Methodol. 11: 46-56 (2018) - Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - 2017
- Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama:
Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement. IPSJ Trans. Syst. LSI Des. Methodol. 10: 28-38 (2017) - Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze:
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. 10: 45-62 (2017) - Yusuke Matsunaga:
An Accelerating Technique for SAT-based ATPG. IPSJ Trans. Syst. LSI Des. Methodol. 10: 39-44 (2017) - Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li:
An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters. IPSJ Trans. Syst. LSI Des. Methodol. 10: 13-27 (2017) - Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 10: 1 (2017) - Xiaoqing Xu, David Z. Pan:
Toward Unidirectional Routing Closure in Advanced Technology Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 10: 2-12 (2017) - Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10: 63-70 (2017)
