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ORCID22nd LATS 2021: Punta del Este, Uruguay
- 22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021. IEEE 2021, ISBN 978-1-6654-2057-0
- Tiago R. Balen, Carlos J. González
, Ingrid F. V. Oliveira, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. de Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen:
Reliability Evaluation of Voters for Fault Tolerant Approximate Systems. 1-6 - Samuel Pagliarini:
A Tutorial on Design Obfuscation: from Transistors to Systems. 1-3 - Hassan El Badawi, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzèrho, François Lefèvre:
Exploring on-line RF performance monitoring based on the indirect test strategy. 1-7 - Mohammadreza Rezaei, Francisco J. Franco, Juan Carlos Fabero, Hortensia Mecha, Helmut Puchner, Juan Antonio Clemente:
Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs. 1-6 - Hassen Aziza, Karine Coulié, Wenceslas Rahajandraibe:
Design Considerations Towards Zero-Variability Resistive RAMs in HRS State. 1-5 - Nunzio Mirabella, Michelangelo Grosso, Giovanna Franchino, Salvatore Rinaudo, Ioannis Deretzis, Antonino La Magna, Matteo Sonza Reorda:
Comparing different solutions for testing resistive defects in low-power SRAMs. 1-6 - Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. 1-6 - Fabrice Pancher, Vanessa Vargas, Pablo Ramos, Rodrigo Possamai Bastos, David César Ardiles Saravia, Raoul Velazco:
Nanosatellite On-Board Computer including a Many-Core Processor. 1-6 - E. Brum, Moritz Fieback, Thiago Santos Copetti, H. Jiayi, Said Hamdioui, Fabian Vargas, Letícia Maria Veiras Bolzani:
Evaluating the Impact of Process Variation on RRAMs. 1-6 - João Paulo Brum, T. Kraemer Sartori, J. Lin, Matheus Garay Trindade, Hassen Fourati, Raoul Velazco, Rodrigo Possamai Bastos:
Evaluation of Attitude Estimation Algorithm under Soft Error Effects. 1-5 - Bernardo Borges Sandoval, Leonardo Heitich Brendler, Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis, Cristina Meinhardt:
Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study. 1-6 - Orlando Verducci Jr., Duarte Lopes de Oliveira, Robson L. Moreno:
Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. 1-6 - Annachiara Ruospo, Lucas Matana Luza, Alberto Bosio, Marcello Traiola, Luigi Dilillo, Ernesto Sánchez:
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks. 1-5 - Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alberto Bosio:
Approximate Computing for Safety-Critical Applications. 1-3 - Tobias Faller, Philipp Scholl, Tobias Paxian, Bernd Becker:
Towards SAT-Based SBST Generation for RISC-V Cores. 1-2 - Sebastian Carbonetto, Luciano Genovese, Lucas Sambuco Salomone, Mariano Garcia Inza, Eduardo Gabriel Redin, Adrián Faigón:
Total Ionizing Dose Effects on Floating Gate Structures. Preliminary Results. 1-6 - Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich:
Resistive Open Defect Classification of Embedded Cells under Variations. 1-6 - Carlos Bernal, Manuel Jiménez, Fabio Andrade:
TLP Generator Setup for Reliable Switching Characterization of Commercial GaN HEMTs. 1-3 - Tommaso Melis, Emmanuel Simeu, Etienne Auvray, Luc Saury:
Improved Fault Diagnosis of Analog Circuits using Light Emission Measures. 1-6 - Karine Coulié, Hassen Aziza, Wenceslas Rahajandraibe:
Investigation of Single Event Effects in a Resistive RAM memory array by SPICE level simulation. 1-6 - Alexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Augusto Pedraza:
Reliability Evaluation of RISC-V and ARM Microprocessors Through a New Fault Injection Tool. 1-6 - Ievgen Kabin, Zoya Dyka, Dan Klann, Peter Langendoerfer:
EC Scalar Multiplication: Successful Simple Address-Bit SCA Attack against Atomic Patterns. 1-2 - Juan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente:
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles. 1-6 - Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis, Cristina Meinhardt:
SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology. 1-2
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