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2020 – today
- 2023
[c15]Richard Panek, Jakub Lojda:
The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller. LASCAS 2023: 1-4- 2021
- [c14]Jakub Lojda, Richard Panek, Zdenek Kotásek:
Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. DSD 2021: 549-552 - [c13]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. DSD 2021: 553-556 - [c12]Jakub Lojda, Richard Panek, Zdenek Kotásek:
Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. EWDTS 2021: 1-8 - [c11]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS 2021: 1-6 - 2020
- [c10]Jakub Lojda, Jakub Podivinsky, Ondrej Cekan
, Richard Panek, Martin Krcma, Zdenek Kotásek:
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS 2020: 1-4 - [c9]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD 2020: 680-683 - [c8]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS 2020: 1-5 - [c7]Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS 2020: 1-4 - [c6]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c5]Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek:
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD 2019: 506-513 - 2018
- [c4]Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD 2018: 244-251 - [c3]Ondrej Cekan, Richard Panek, Zdenek Kotásek:
Input and Output Generation for the Verification of ALU: A Use Case. EWDTS 2018: 1-6 - [c2]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. EWDTS 2018: 1-6 - 2017
- [c1]Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD 2017: 337-344
Coauthor Index
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