• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 71 matches

• 2004
• 
  Indrajit Atluri, Tughrul Arslan:
  Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation. ISVLSI 2004: 215-217
• 
  Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos:
  Scan Cell Ordering for Low Power BIST. ISVLSI 2004: 281-284
• 
  Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
  Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. ISVLSI 2004: 222-225
• 
  Debayan Bhaduri, Sandeep K. Shukla:
  NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures. ISVLSI 2004: 25-31
• 
  Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine:
  Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. ISVLSI 2004: 237-238
• 
  Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis:
  Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ISVLSI 2004: 127-134
• 
  Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao:
  64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ISVLSI 2004: 233-236
• 
  Lerong Cheng, William N. N. Hung, Guowu Yang, Xiaoyu Song:
  Congestion Estimation for 3D Routing. ISVLSI 2004: 239-240
• 
  Shu-Shin Chin, Sangjin Hong, Suhwan Kim:
  Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. ISVLSI 2004: 158-166
• 
  Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
  Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI 2004: 243-248
• 
  Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou:
  Experimental Evaluation of Resonant Clock Distribution. ISVLSI 2004: 135-140
• 
  Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin:
  A Memory Aware High Level Synthesis Tool . ISVLSI 2004: 279-280
• 
  W. Rhett Davis, Ambarish M. Sule, Hao Hua:
  Multi-Parameter Power Minimization of Synthesized Datapaths. ISVLSI 2004: 151-157
• 
  Abdel Ejnioui, Abdelhalim Alsharqawi:
  Pipeline Design Based on Self-Resetting Stage Logic. ISVLSI 2004: 254-257
• 
  Abdel Ejnioui, Abdelkader Rhiati:
  A Reconfigurable Memory Management Core for Java Applications. ISVLSI 2004: 309-312
• 
  Walid Elgharbawy, Magdy A. Bayoumi:
  New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui. ISVLSI 2004: 115-120
• 
  Ahmet T. Erdogan, Tughrul Arslan:
  Low Power FIR Filter Implementations Based on Coefficient Ordering Algorithm. ISVLSI 2004: 226-228
• 
  Benjamin Gojman, Eric Rachlin, John E. Savage:
  Decoding of Stochastically Assembled Nanoarrays. ISVLSI 2004: 11-18
• 
  Mahadevan Gomathisankaran, Akhilesh Tyagi:
  WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays. ISVLSI 2004: 105-114
• 
  Chandramouli Gopalakrishnan, Srinivas Katkoori:
  Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. ISVLSI 2004: 260-261
• 
  Venu G. Gudise, Ganesh K. Venayagamoorthy:
  FPGA Placement and Routing Using Particle Swarm Optimization. ISVLSI 2004: 307-308
• 
  Kristian Hildingsson, Tughrul Arslan, Ahmet T. Erdogan:
  Energy Evaluation Methodology for Platform Based System-on-Chip Design. ISVLSI 2004: 61-68
• 
  Alireza Hodjat, Ingrid Verbauwhede:
  Minimum Area Cost for a 30 to 70 Gbits/s AES Processor. ISVLSI 2004: 83-88
• 
  Sangjin Hong, Shu-Shin Chin:
  Incorporating Power Reduction Mechanism in Arithmetic Core Design. ISVLSI 2004: 249-250
• 
  Nick Iliev, James E. Stine, Nathan Jachimiec:
  Parallel Programmable Finite Field GF(2m) Multipliers. ISVLSI 2004: 299-302
• 
  Krzysztof Iniewski, Marek Syrzycki:
  Low Power 2.5 Gb/s Serializer for SOC Applications. ISVLSI 2004: 211-212
• 
  Suryaprasad Jayadevappa, Ravi Shankar, Imad Mahgoub:
  A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study. ISVLSI 2004: 52-60
• 
  Sankalp Kallakuri, Alex Doboli, Simona Doboli:
  Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies. ISVLSI 2004: 199-206
• 
  Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
  An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI 2004: 285-288
• 
  Robert D. Kenney, Michael J. Schulte:
  Multioperand Decimal Addition. ISVLSI 2004: 251-253

skipping 41 more matches