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2020 – today
- 2024
[j4]Ming-I Brandon Lin
, Bonnie Wu, Shun-Wen Cheng:
Changes in Navigation Controls and Field-of-View Modes Affect Cybersickness Severity and Spatiotemporal Gait Patterns After Exposure to Virtual Environments. Hum. Factors 66(7): 1942-1960 (2024)
2010 – 2019
- 2018
- [c14]Shun-Wen Cheng, Chun-Pin Lin, Chi-Shi Chen, Wei-Chang Tsai:
Universal CMOS Diamond-Graph Circuit for Embedded Computing. SoCC 2018: 206-212 - 2016
- [c13]Chun-Yao Shih, Shun-Wen Cheng:
A driver's physiological monitoring system based on photodiode sensor with reflective optics element. ICVES 2016: 1-4 - [c12]Shun-Wen Cheng:
Self-dual diamond-graph CMOS H-bridge logic family. SoCC 2016: 300-305 - 2014
- [c11]Yong-Xiang Chen, Siek-Siang Chiang, Shu-Yun Chih, Wen-Ching Liao, Shih-Yao Lin, Shang-Hua Yang, Shun-Wen Cheng, Shih-Sung Lin, Yu-Shan Lin, Ming-Sui Lee, Jau-Yih Tsauo, Cheng-Min Jen, Chia-Shiang Shih, King-Jen Chang, Yi-Ping Hung:
Opportunities for Persuasive Technology to Motivate Heavy Computer Users for Stretching Exercise. PERSUASIVE 2014: 25-30 - 2010
- [c10]Shun-Wen Cheng:
Over complementary MOS logic for don't care conditions. APCCAS 2010: 700-703
2000 – 2009
- 2008
- [c9]Shun-Wen Cheng:
H-tree CMOS logic circuit. ICECS 2008: 542-545 - 2006
- [j3]Kuo-Hsing Cheng, Shun-Wen Cheng, Wen-Shiuan Lee:
64-bit Pipeline Carry Lookahead Adder Using all-n-transistor Tspc Logics. J. Circuits Syst. Comput. 15(1): 13-28 (2006) - [j2]Kuo-Hsing Cheng, Shun-Wen Cheng:
Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications. J. Inf. Sci. Eng. 22(4): 975-989 (2006) - 2005
- [j1]Kuo-Hsing Cheng, Shun-Wen Cheng:
64-Bit High-Performance Power-Aware Conditional Carry Adder Design. IEICE Trans. Electron. 88-C(6): 1322-1331 (2005) - 2004
- [c8]Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao:
64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. ISVLSI 2004: 233-236 - [c7]Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang:
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC 2004: 65-68 - 2003
- [c6]Shun-Wen Cheng:
Arbitrary long digit integer sorter HW/SW co-design. ASP-DAC 2003: 538-543 - [c5]Shun-Wen Cheng:
A high-speed magnitude comparator with small transistor count. ICECS 2003: 1168-1171 - 2002
- [c4]Kuo-Hsing Cheng, Shun-Wen Cheng:
Influences of minimum cut plane properties on the mincut circuit partitioning problems. ICECS 2002: 375-379 - [c3]Kuo-Hsing Cheng, Shun-Wen Cheng:
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. ASP-DAC/VLSI Design 2002: 155-159 - 2001
- [c2]Kuo-Hsing Cheng, Shun-Wen Cheng:
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning. ICECS 2001: 889-893 - [c1]Shun-Wen Cheng, Kuo-Hsing Cheng:
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. ISCAS (5) 2001: 167-170
Coauthor Index
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