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ORCIDDimitris Bakalis
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2010 – 2019
- 2015
[j13]Haridimos T. Vergos, Dimitris Bakalis
, A. Anastasiou:
Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Syst. Signal Process. 34(4): 1041-1056 (2015)- 2013
- [c28]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Reverse converters for RNSs with diminished-one encoded channels. EUROCON 2013: 1798-1805 - [c27]Evangelos Vassalos, Dimitris Bakalis:
Modulo 2n-2 arithmetic units. EUROCON 2013: 1806-1813 - [c26]Evangelos Vassalos, Dimitris Bakalis:
On the design of modulo 2n-1 cubing units. ACM Great Lakes Symposium on VLSI 2013: 251-256 - [c25]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
RNS assisted image filtering and edge detection. DSP 2013: 1-6 - 2012
- [j12]Haridimos T. Vergos, Dimitris Bakalis:
Area-time efficient multi-modulus adders and their applications. Microprocess. Microsystems 36(5): 409-419 (2012) - [j11]Evangelos Vassalos, Dimitris Bakalis:
CSD-RNS-based Single Constant Multipliers. J. Signal Process. Syst. 67(3): 255-268 (2012) - [c24]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Residue-to-Binary Converters Design. DSD 2012: 65-72 - 2011
- [j10]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. Circuits Syst. Signal Process. 30(6): 1445-1461 (2011) - [j9]Dimitris Bakalis, Haridimos T. Vergos, Anastasia Spyrou:
Efficient modulo 2n±1 squarers. Integr. 44(3): 163-174 (2011) - [c23]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. DSD 2011: 468-475 - [c22]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
On the use of double-LSB and signed-LSB encodings for RNS. DSP 2011: 1-6 - 2010
- [j8]Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou:
Fast modulo 2n+1 multi-operand adders and residue generators. Integr. 43(1): 42-48 (2010) - [j7]Haridimos T. Vergos, Dimitris Bakalis:
On Implementing Efficient Modulo 2n + 1 Arithmetic Components. J. Circuits Syst. Comput. 19(5): 911-930 (2010) - [c21]Dimitris Bakalis, Haridimos T. Vergos:
Area-Efficient Multi-moduli Squarers for RNS. DSD 2010: 408-411 - [c20]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Forward and Reverse Converters. ISVLSI 2010: 11-16 - [c19]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
SUT-RNS Forward and Reverse Converters. ISVLSI (Selected papers) 2010: 231-244
2000 – 2009
- 2009
- [j6]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. 14(2): 28:1-28:15 (2009) - [c18]Evangelos Vassalos, Dimitris Bakalis:
Combined SD-RNS Constant Multiplication. DSD 2009: 172-179 - [c17]Anastasia Spyrou, Dimitris Bakalis, Haridimos T. Vergos:
Efficient architectures for modulo 2n-1 squares. DPS 2009: 1-6 - [c16]Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
Novel modulo 2n+1 subtractors. DPS 2009: 1-5 - 2008
- [c15]Haridimos T. Vergos, Dimitris Bakalis:
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. DSD 2008: 752-759 - [c14]Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou:
Efficient modulo 2n + 1 multi-operand adders. ICECS 2008: 694-697 - 2006
- [j5]Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos:
A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. 52(1): 1-12 (2006) - 2004
- [c13]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos:
Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED 2004: 205-210 - [c12]Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos:
Scan Cell Ordering for Low Power BIST. ISVLSI 2004: 281-284 - [c11]Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos:
An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI 2004: 285-288 - 2002
- [j4]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. 18(3): 315-332 (2002) - [j3]Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou:
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. 48(4-5): 125-135 (2002) - [j2]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 859-866 (2002) - [c10]Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis:
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW 2002: 152-157 - [c9]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED 2002: 261-266 - 2001
- [b1]Dimitris Bakalis:
Δομές ενσωματωμένου αυτοελέγχου για ψηφιακά κυκλώματα πολύ μεγάλης κλίμακας ολοκλήρωσης. University of Patras, Greece, 2001 - [j1]Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou:
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design 12(3): 431-448 (2001) - [c8]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI 2001: 7-12 - [c7]Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW 2001: 80-86 - [c6]Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos:
On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW 2001: 153-157 - [c5]Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED 2001: 350-355 - [c4]Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, Dimitrios Lymperopoulos:
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. IEEE International Workshop on Rapid System Prototyping 2001: 182-187 - 2000
- [c3]Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos:
Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED 2000: 433-438 - [c2]Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos:
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC 2000: 804-811
1990 – 1999
- 1999
- [c1]Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou:
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT 1999: 121-129
Coauthor Index
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