• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 53 matches

• 2006
• 
  Vikas Aggarwal, Alan D. George, K. Clint Slatton:
  Reconfigurable computing with multiscale data fusion for remote sensing. FPGA 2006: 235
• 
  Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier:
  An adaptive Reed-Solomon errors-and-erasures decoder. FPGA 2006: 150-158
• 
  Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert:
  Embedded floating-point units in FPGAs. FPGA 2006: 12-20
• 
  Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon:
  Magnetic tunnelling junction based FPGA. FPGA 2006: 123-130
• 
  Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
  Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100
• 
  Young H. Cho, James Moscola, John W. Lockwood:
  Context-free-grammar based token tagger in reconfigurable devices. FPGA 2006: 237
• 
  Jike Chong, Chidamber Kulkarni, Gordon J. Brebner:
  Building a flexible and scalable DRAM interface for networking applications on FPGAs. FPGA 2006: 233
• 
  Christopher R. Clark, David E. Schimmel:
  Modeling the data-dependent performance of pattern-matching architectures. FPGA 2006: 73-82
• 
  Jason Cong, Kirill Minkovich:
  Optimality study of logic synthesis for LUT-based FPGAs. FPGA 2006: 33-40
• 
  Nathaniel Couture, Kenneth B. Kent:
  Periodic licensing of FPGA based intellectual property. FPGA 2006: 234
• 
  Kenneth Eguro, Scott Hauck:
  Armada: timing-driven pipeline-aware routing for FPGAs. FPGA 2006: 169-178
• 
  Wenyi Feng, Jonathan W. Greene:
  Post-placement interconnect entropy. FPGA 2006: 227
• 
  Michael P. Gilroy, James Irvine, William Berrie:
  FPGA based RAID 6 hardware accelerator. FPGA 2006: 232
• 
  Youngsun Han, Seokjoong Hwang, Seon Wook Kim:
  Jaguar: a compiler infrastructure for Java reconfigurable computing. FPGA 2006: 228
• 
  Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
  Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223
• 
  Mark Holland, Scott Hauck:
  Improving performance and robustness of domain-specific CPLDs. FPGA 2006: 50-59
• 
  Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu:
  Design, implementation, and verification of active cache emulator (ACE). FPGA 2006: 63-72
• 
  Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi:
  Effective clustering technique to optimize routability of outer cluster nets. FPGA 2006: 229
• 
  Ian Kuon, Jonathan Rose:
  Measuring the gap between FPGAs and ASICs. FPGA 2006: 21-30
• 
  Julien Lamoureux, Steven J. E. Wilton:
  FPGA clock network architecture: flexibility vs. area and power. FPGA 2006: 101-108
• 
  Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong:
  Performance benefits of monolithically stacked 3D-FPGA. FPGA 2006: 113-122
• 
  Jianhua Liu, Michael Chang, Chung-Kuan Cheng:
  An iterative division algorithm for FPGAs. FPGA 2006: 83-89
• 
  Yohei Matsumoto, Hanpei Koike, Akira Masaki:
  FPGAs with multidimensional mesh topology. FPGA 2006: 223
• 
  Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis:
  A reconfigurable hardware based embedded scheduler for buffered crossbar switches. FPGA 2006: 143-149
• 
  Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel:
  Fast and accurate resource estimation of automatically generated custom DFT IP cores. FPGA 2006: 211-220
• 
  Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner:
  High speed FIR filter implementation using add and shift method. FPGA 2006: 231
• 
  Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
  Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49
• 
  Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
  A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225
• 
  Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura:
  Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. FPGA 2006: 224
• 
  David T. Nguyen, Gokhan Memik, Alok N. Choudhary:
  A reconfigurable architecture for network intrusion detection using principal component analysis. FPGA 2006: 235

skipping 23 more matches