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ORCIDHayder Mrabet
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2000 – 2009
- 2009
[b1]Hayder Mrabet:
Design and Optimization of Reconfigurable Architectures: The FPGA Family. (Conception et optimisation d'architectures reconfigurables de type FPGA). Pierre and Marie Curie University, Paris, France, 2009- [j1]Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez:
FPGA Interconnect Topologies Exploration. Int. J. Reconfigurable Comput. 2009: 259837:1-259837:13 (2009) - [c13]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794 - [c12]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206 - 2008
- [c11]Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez:
Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326 - [c10]Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120 - 2007
- [c9]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Efficient Mesh of Tree Interconnect for FPGA Architecture. FPT 2007: 269-272 - [c8]Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez:
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS 2007: 243-252 - 2006
- [c7]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225 - [c6]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Configuration tools for a new multilevel hierarchical FPGA. FPGA 2006: 229 - [c5]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez:
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD 2006: 675-679 - [c4]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI 2006: 263-268 - [c3]Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot:
Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006: 117-123 - 2005
- [c2]Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig 2005 - [c1]Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot:
Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005: 59-62
Coauthor Index
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