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2010 – 2019
- 2017
[j4]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious
, Mohamed Abid, Habib Mehrez:
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. Turkish J. Electr. Eng. Comput. Sci. 25: 2044-2054 (2017)- [c20]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. HPCS 2017: 572-579 - 2016
- [j3]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, Habib Mehrez:
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocess. Microsystems 40: 16-26 (2016) - [c19]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. IDT 2016: 31-36 - [c18]Sonda Chtourou, Mohamed Abid, Zied Marrakchi, Emna Amouri, Habib Mehrez:
The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. HPCS 2016: 104-111 - [c17]Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Habib Mehrez, Mohamed Abid:
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. PDP 2016: 635-642 - 2015
- [c16]Sonda Chtourou, Zied Marrakchi, Vinod Pangracious, Emna Amouri, Habib Mehrez, Mohamed Abid:
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. ARC 2015: 411-418 - [c15]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT 2015: 1-4 - 2014
- [j2]Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Architecture level optimization of 3-dimensional tree-based FPGA. Microelectron. J. 45(4): 355-366 (2014) - [c14]Sonda Chtourou, Mohamed Abid, Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez:
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. 3DIC 2014: 1-7 - [c13]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014: 1-4 - [c12]Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. FPL 2014: 1-4 - [c11]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi:
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - [c10]Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. ReConFig 2014: 1-6 - 2013
- [j1]Emna Amouri, Habib Mehrez, Zied Marrakchi:
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. Int. J. Reconfigurable Comput. 2013: 802436:1-802436:24 (2013) - [c9]Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez:
Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. ARC 2013: 197-209 - [c8]Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi:
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT 2013: 434-437 - [c7]Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi:
Physical design exploration of 3D tree-based FPGA architecture. ACM Great Lakes Symposium on VLSI 2013: 335-336 - [c6]Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi:
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig 2013: 1-6 - 2011
- [c5]Emna Amouri, Zied Marrakchi, Habib Mehrez:
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC 2011: 1-4 - 2010
- [c4]Emna Amouri, Zied Marrakchi, Habib Mehrez:
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS 2010: 296-299
2000 – 2009
- 2009
- [c3]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794 - [c2]Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez:
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206 - 2008
- [c1]Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez:
Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326
Coauthor Index
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