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ORCIDRoselyne Chotin-Avot
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2010 – 2019
- 2019
[c24]Julian Leonhard, Muhammad Yasin
, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Louërat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos:
MixLock: Securing Mixed-Signal Circuits via Logic Locking. DATE 2019: 84-89- 2018
- [j6]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Habib Mehrez:
Novel architectural space exploration environment for multi-FPGA based prototyping systems. Microprocess. Microsystems 56: 169-183 (2018) - 2017
- [j5]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. J. Signal Process. Syst. 88(1): 1-12 (2017) - 2016
- [c23]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Zouha Cherif, Maminionja Ravoson, Saqib Khan, Habib Mehrez:
Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. DSD 2016: 641-645 - [c22]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. CS2@HiPEAC 2016: 37-40 - [c21]Muhammad Moazam Azeem, Roselyne Chotin-Avot, Umer Farooq, Maminionja Ravoson, Habib Mehrez:
Multiple FPGAs based prototyping and debugging with complete design flow. IDT 2016: 171-176 - [c20]Umer Farooq, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Mariem Turki, Habib Mehrez:
Inter-FPGA routing environment for performance exploration of multi-FPGA systems. RSP 2016: 107-113 - 2014
- [j4]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Low cost solutions for secure remote reconfiguration of FPGAs. Int. J. Embed. Syst. 6(2/3): 257-265 (2014) - [j3]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Authenticated encryption on FPGAs from the static part to the reconfigurable part. Microprocess. Microsystems 38(6): 526-538 (2014) - [c19]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. ARC 2014: 13-24 - [c18]Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang:
Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). FPGA 2014: 242 - [c17]Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. FPL 2014: 1-4 - [c16]Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi:
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. ISVLSI 2014: 553-558 - [c15]Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
A reference-based specification tool for creating reliable library development specifications. NEWCAS 2014: 133-136 - [c14]Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri:
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. ReConFig 2014: 1-6 - 2013
- [j2]Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez:
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. Integr. 46(2): 104-118 (2013) - [c13]Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi:
A defect-tolerant cluster in a mesh SRAM-based FPGA. FPT 2013: 434-437 - [c12]Jung Kyu Chae, Severine Bertrand, Pierre-Francois Ollagnon, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
Efficient state-dependent power model for multi-bit flip-flop banks. MWSCAS 2013: 461-464 - [c11]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Efficient AES-GCM for VPNs using FPGAs. MWSCAS 2013: 1411-1414 - [c10]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Protecting FPGA bitstreams using authenticated encryption. NEWCAS 2013: 1-4 - [c9]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Lightweight and compact solutions for secure reconfiguration of FPGAs. ReConFig 2013: 1-4 - [c8]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Improved method for parallel AES-GCM cores using FPGAs. ReConFig 2013: 1-4 - [c7]Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi:
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. ReConFig 2013: 1-6 - [c6]Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez:
A formalism of the specifications for library development. SoCC 2013: 307-312 - [c5]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
High speed authenticated encryption for slow changing key applications using reconfigurable devices. Wireless Days 2013: 1-6 - 2012
- [c4]Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez:
Efficient parallel-pipelined GHASH for message authentication. ReConFig 2012: 1-6 - 2011
- [c3]Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez:
Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. ISQED 2011: 502-507
2000 – 2009
- 2008
- [c2]Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez:
Arithmetic Data Path Optimization Using Borrow-Save Representation. ISVLSI 2008: 4-9 - 2006
- [c1]Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade:
MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation. ReCoSoC 2006: 24-30 - 2004
- [j1]Roselyne Avot-Chotin, Habib Mehrez:
Hardware Implementation of Discrete Stochastic Arithmetic. Numer. Algorithms 37(1-4): 21-33 (2004) - 2003
- [b1]Roselyne Chotin-Avot:
Architectures matérielles pour l'arithmétique stochastique discrète. (Hardware architecture for discrete stochastic arithmetic). Pierre and Marie Curie University, Paris, France, 2003
Coauthor Index
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