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Publication search results
found 46 matches
- 2011
- Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel:
Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors. CODES+ISSS 2011: 365-374 - Junwhan Ahn, Kiyoung Choi:
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. CODES+ISSS 2011: 345-354 - Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, Drew Wingard:
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends. CODES+ISSS 2011: 3-12 - Philip Axer, Maurice Sebastian, Rolf Ernst:
Reliability analysis for MPSoCs with mixed-critical, hard real-time constraints. CODES+ISSS 2011: 149-158 - Luis Angel D. Bathen, Nikil D. Dutt, Dongyoun Shin, Sung-Soo Lim:
SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories. CODES+ISSS 2011: 79-88 - Garo Bournoutian, Alex Orailoglu:
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors. CODES+ISSS 2011: 89-98 - Krishnendu Chakrabarty, Paul Pop, Tsung-Yi Ho:
Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems. CODES+ISSS 2011: 377-378 - Ted Chang:
ESWEEK industry keynote: embedding the cloud. CODES+ISSS 2011: 379-380 - Yu-Ting Chen, Jason Cong, Glenn Reinman:
HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. CODES+ISSS 2011: 295-304 - Zefu Dai, Jianwen Zhu:
A bursty multi-port memory controller with quality-of-service guarantees. CODES+ISSS 2011: 21-28 - Thomas Ebi, David Kramer, Wolfgang Karl, Jörg Henkel:
Economic learning for thermal-aware power budgeting in many-core architectures. CODES+ISSS 2011: 189-196 - Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy:
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS 2011: 39-48 - Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu, El Mostapha Aboulhamid:
A linear-time approach for the transient thermal simulation of liquid-cooled 3d ics. CODES+ISSS 2011: 197-206 - Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi:
Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations. CODES+ISSS 2011: 257-266 - Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich:
Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78 - Tsung-Yi Ho, Krishnendu Chakrabarty, Paul Pop:
Digital microfluidic biochips: recent research and emerging challenges. CODES+ISSS 2011: 335-344 - Jia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois C. Knoll:
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems. CODES+ISSS 2011: 247-256 - Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfgang Schröder-Preikschat, Jörg Henkel:
DistRM: distributed resource management for on-chip many-core systems. CODES+ISSS 2011: 119-128 - Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar:
Exploiting temporal decoupling to accelerate trace-driven NoC emulation. CODES+ISSS 2011: 315-324 - Pratyush Kumar, Lothar Thiele:
System-level power and timing variability characterization to compute thermal guarantees. CODES+ISSS 2011: 179-188 - Kai Lampka, Kai Huang, Jian-Jia Chen:
Dynamic counters and the efficient and effective online power management of embedded real-time systems. CODES+ISSS 2011: 267-276 - Kuen-Jong Lee, Chin-Yao Chang, I-Jou Chen:
EPIDETOX: an ESL platform for integrated circuit design and tool exploration. CODES+ISSS 2011: 381-384 - Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh:
System-level design exploration for 3-D stacked memory architectures. CODES+ISSS 2011: 389-390 - Jane W.-S. Liu:
To alert, rescue and recover: critical information technologies for managing mega disasters. CODES+ISSS 2011: 1-2 - Jing Lu, Yooseong Kim, Aviral Shrivastava, Chuan Huang:
Branch penalty reduction on IBM cell SPUs via software branch hinting. CODES+ISSS 2011: 355-364 - Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang:
Mapping of applications to MPSoCs. CODES+ISSS 2011: 109-118 - Alejandro Masrur, Thomas Pfeuffer, Martin Geier, Sebastian Drössler, Samarjit Chakraborty:
Designing VM schedulers for embedded real-time applications. CODES+ISSS 2011: 29-38 - Benjamin Menhorn, Frank Slomka:
Design entropy concept: a measurement for complexity. CODES+ISSS 2011: 285-294 - Moustafa Mohamed, Zheng Li, Xi Chen, Alan Rolf Mickelson, Li Shang:
Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems. CODES+ISSS 2011: 227-236 - Linwei Niu, Wei Li:
Energy-efficient fixed-priority scheduling for real-time systems based on threshold work-demand analysis. CODES+ISSS 2011: 159-168
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