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Tali Moreshet
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2020 – today
- 2022
- [c19]Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. HPEC 2022: 1-6 - [c18]Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. SPAA 2022: 321-332 - 2020
- [j7]Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu:
Voltage Noise Mitigation With Barrier Approximation. IEEE Comput. Archit. Lett. 19(2): 155-158 (2020)
2010 – 2019
- 2019
- [c17]Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar:
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. DATE 2019: 1571-1574 - [c16]Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu:
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. IISWC 2019: 263-267 - [c15]Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Attacking memory-hard scrypt with near-data-processing. MEMSYS 2019: 33-37 - [c14]Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. SPAA 2019: 297-308 - 2018
- [j6]Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. Int. J. Parallel Program. 46(6): 1304-1328 (2018) - 2017
- [j5]Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. ACM Trans. Embed. Comput. Syst. 16(5s): 153:1-153:18 (2017) - [c13]Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar:
Evaluating critical bits in arithmetic operations due to timing violations. HPEC 2017: 1-7 - 2016
- [c12]Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar:
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. CASES 2016: 20:1-20:10 - 2015
- [j4]Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. ACM Trans. Embed. Comput. Syst. 14(3): 51:1-51:27 (2015) - [c11]Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. ACM Great Lakes Symposium on VLSI 2015: 9-14 - 2014
- [c10]Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Speculative synchronization for coherence-free embedded NUMA architectures. ICSAMOS 2014: 99-106 - 2013
- [c9]Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini:
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. MES 2013: 58-61 - 2011
- [c8]Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy:
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS 2011: 39-48 - [c7]Fuat Keceli, Tali Moreshet, Uzi Vishkin:
Power-Performance Comparison of Single-Task Driven Many-Cores. ICPADS 2011: 348-355 - 2010
- [j3]Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. J. Parallel Distributed Comput. 70(10): 1042-1052 (2010) - [c6]Fuat Keceli, Tali Moreshet, Uzi Vishkin:
Thermal Management of a Many-Core Processor under Fine-Grained Parallelism. Euro-Par Workshops (1) 2010: 249-259 - [c5]Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. HiPEAC 2010: 50-65
2000 – 2009
- 2008
- [c4]Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI 2008: 435-440 - 2007
- [j2]Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy:
A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Comput. Archit. News 35(1): 47-54 (2007) - 2006
- [c3]Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy implications of multiprocessor synchronization. SPAA 2006: 329 - 2005
- [c2]Tali Moreshet, R. Iris Bahar, Maurice Herlihy:
Energy reduction in multiprocessor systems using transactional memory. ISLPED 2005: 331-334 - 2004
- [j1]Tali Moreshet, R. Iris Bahar:
Effects of speculation on performance and issue queue design. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1123-1126 (2004) - 2003
- [c1]Tali Moreshet, R. Iris Bahar:
Power-aware issue queue design for speculative instructions. DAC 2003: 634-637
Coauthor Index
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