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Dimitra Papagiannopoulou

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2010 – 2019

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2019
[c8]
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Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar:
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. DATE 2019: 1571-1574
2018
[j4]
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Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. Int. J. Parallel Program. 46(6): 1304-1328 (2018)
2017
[j3]
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Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. ACM Trans. Embed. Comput. Syst. 16(5s): 153:1-153:18 (2017)
[c7]
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Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar:
Evaluating critical bits in arithmetic operations due to timing violations. HPEC 2017: 1-7
2016
[c6]
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Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar:
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. CASES 2016: 20:1-20:10
2015
[j2]
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Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar:
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. ACM Trans. Embed. Comput. Syst. 14(3): 51:1-51:27 (2015)
[c5]
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Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. ACM Great Lakes Symposium on VLSI 2015: 9-14
2014
[c4]
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Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar:
Speculative synchronization for coherence-free embedded NUMA architectures. ICSAMOS 2014: 99-106
2013
[c3]
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Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini:
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. MES 2013: 58-61
[c2]
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Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar:
Flexible data allocation for scratch-pad memories to reduce NBTI effects. ISQED 2013: 60-67
2012
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Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera:
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electron. Test. 28(3): 349-363 (2012)
2011
[c1]
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Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera:
NBTI-aware data allocation strategies for scratchpad memory based embedded systems. LATW 2011: 1-6

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