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ORCIDYuting Chen 0003
Person information
- affiliation: University of California, Computer Science Department, Los Angeles, CA, USA
Other persons with the same name
- Yuting Chen (aka: Yu-Ting Chen) — disambiguation page
- Yuting Chen 0001
![[0000-0002-4128-8966]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-4128-8966")
— Shanghai Jiao Tong University, School of Electronic Information and Electrical Engineering, Shanghai, China (and 1 more) - Yuting Chen 0002 (aka: Yu-Ting Chen 0002) — Google Research, Mountain View, CA, USA (and 1 more)
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2010 – 2019
- 2016
[b2]Yu-Ting Chen:
Memory System Optimizations for Customized Computing - From Single-Chip to Datacenter. University of California, Los Angeles, USA, 2016- [c12]Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei:
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. FCCM 2016: 29 - [c11]Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu:
The SMEM Seeding Acceleration for DNA Sequence Alignment. FCCM 2016: 32-39 - [c10]Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong:
A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). FPGA 2016: 277 - [c9]Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). FPGA 2016: 281 - [c8]Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei:
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. HotCloud 2016 - [i1]Yu-Ting Chen, Jason Cong, Zhenman Fang, Bingjun Xiao, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. CoRR abs/1610.09761 (2016) - 2015
- [b1]Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao:
Customizable Computing. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2015, ISBN 978-3-031-00620-3 - [c7]Yu-Ting Chen, Jason Cong, Jie Lei, Peng Wei:
A Novel High-Throughput Acceleration Engine for Read Alignment. FCCM 2015: 199-202 - [c6]Yu-Ting Chen, Jason Cong:
Interconnect synthesis of heterogeneous accelerators in a shared memory architecture. ISLPED 2015: 359-364 - [c5]Yu-Ting Chen, Jason Cong, Bingjun Xiao:
ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. ISPASS 2015: 157-158 - 2013
- [c4]Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou:
Accelerator-rich CMPs: From concept to real hardware. ICCD 2013: 169-176 - 2012
- [c3]Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman:
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. DATE 2012: 45-50 - [c2]Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar, Glenn Reinman:
Static and dynamic co-optimizations for blocks mapping in hybrid caches. ISLPED 2012: 237-242 - 2011
- [c1]Yu-Ting Chen, Jason Cong, Glenn Reinman:
HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. CODES+ISSS 2011: 295-304
Coauthor Index
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