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Publication search results
found 39 matches
- 2008
- Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135 - Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele:
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158 - Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro:
Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems. ARC 2008: 111-123 - Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet:
A Networked, Lightweight and Partially Reconfigurable Platform. ARC 2008: 314-319 - Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A Parallel Hardware Architecture for Image Feature Detection. ARC 2008: 136-147 - Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 - Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez:
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture. ARC 2008: 332-337 - Haruna Cofer, Matthias Fouquet-Lapar, Timothy Gamerdinger, Christopher Lindahl, Bruce Losure, Alan Mayer, James Swoboda, Teruo Utsumi:
Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable ALTIX System Infrastructure and Benchmarking Life-Science Applications. ARC 2008: 266-271 - Ozana Silvia Dragomir, Elena Moscu Panainte, Koen Bertels, Stephan Wong:
Optimal Unroll Factor for Reconfigurable Architectures. ARC 2008: 4-14 - Piotr Dziurzanski, Tomasz Maka:
Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on Chip. ARC 2008: 290-295 - Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk:
An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC 2008: 219-230 - Hagen Gädke, Andreas Koch:
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens. ARC 2008: 183-194 - Carlo Galuzzi, Koen Bertels:
The Instruction-Set Extension Problem: A Survey. ARC 2008: 207-218 - Carlo Galuzzi, Koen Bertels:
A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures. ARC 2008: 278-283 - Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich:
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289 - Reiner W. Hartenstein:
The von Neumann Syndrome and the CS Education Dilemma. ARC 2008: 3 - Adriano Idalgo, Nahri Moreano:
DNA Physical Mapping on a Reconfigurable Platform. ARC 2008: 27-38 - Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC 2008: 243-253 - Slavisa Jovanovic, Camel Tanougast, Serge Weber:
A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems. ARC 2008: 159-170 - Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek:
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ARC 2008: 296-301 - Yo-Hsien Lin, Jong-Chen Chen:
Neuromolecularware -- A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis. ARC 2008: 320-325 - Chia-Tien Dan Lo, Yi-Gang Tai:
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs. ARC 2008: 51-62 - Antonio Roldao Lopes, George A. Constantinides:
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. ARC 2008: 75-86 - Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. ARC 2008: 302-307 - Masaki Nakanishi:
An FPGA Configuration Scheme for Bitstream Protection. ARC 2008: 326-331 - Filipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José Carlos Alves:
A Custom Processor for a TDMA Solver in a CFD Application. ARC 2008: 63-74 - Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. ARC 2008: 231-242 - Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker:
Data reallocation by exploiting FPGA configuration mechanisms. ARC 2008: 308-313 - Shane Santner, Wesley Peck, Jason Agron, David Andrews:
Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. ARC 2008: 99-110 - Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto:
Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC 2008: 260-265
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