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ORCIDThomas Marconi
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2010 – 2019
- 2017
[c19]Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin
, Sorin Dan Cotofana:
LDPC-Based Adaptive Multi-Error Correction for 3D Memories. ICCD 2017: 265-268- [c18]Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana:
Low cost multi-error correction for 3D polyhedral memories. NANOARCH 2017: 13-18 - 2015
- [c17]Thomas Marconi, Sorin Cotofana:
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding. ACM Great Lakes Symposium on VLSI 2015: 245-248 - 2014
- [j1]Thomas Marconi:
Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays. Comput. Electr. Eng. 40(4): 1215-1237 (2014) - [c16]Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
Towards energy effective LDPC decoding by exploiting channel noise variability. VLSI-SoC 2014: 1-6 - [c15]Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
Transmission Channel Noise Aware Energy Effective LDPC Decoding. VLSI-SoC (Selected Papers) 2014: 198-219 - 2013
- [c14]Kaushik Triyambaka Mysur, Mihai Pricopi, Thomas Marconi, Tulika Mitra:
Implementation of core coalition on FPGAs. VLSI-SoC 2013: 198-203 - 2012
- [c13]Liang Chen, Thomas Marconi, Tulika Mitra:
Online scheduling for multi-core shared reconfigurable fabric. DATE 2012: 582-585 - 2011
- [b1]Thomas Marconi:
Efficient Runtime Management of Reconfigurable Hardware Resources. Delft University of Technology, Netherlands, 2011 - [c12]Thomas Marconi, Tulika Mitra:
A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs. FPT 2011: 1-6 - 2010
- [c11]Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices. ARC 2010: 194-206 - [c10]Yi Lu, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev:
A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems. FCCM 2010: 65-68 - [c9]Thomas Marconi, Dimitris Theodoropoulos, Koen Bertels, Georgi Gaydadjiev:
A novel HDL coding style to reduce power consumption for reconfigurable devices. FPT 2010: 295-299 - [c8]Thomas Marconi, Jae Young Hur, Koen Bertels, Georgi Gaydadjiev:
A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices. SASP 2010: 87-92
2000 – 2009
- 2009
- [c7]Yi Lu, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev:
Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems. ARC 2009: 216-230 - [c6]Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor P. Stefanov:
Flexible pipelining design for recursive variable expansion. IPDPS 2009: 1-8 - 2008
- [c5]Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices. ARC 2008: 302-307 - [c4]Yi Lu, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels:
An efficient algorithm for free resources management on the FPGA. DATE 2008: 1095-1098 - [c3]Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems. DATE 2008: 1346-1351 - [c2]Yi Lu, Thomas Marconi, Georgi Gaydadjiev, Koen Bertels, Roel Meeuws:
A self-adaptive on-line task placement algorithm for partially reconfigurable systems. IPDPS 2008: 1-8 - 2007
- [c1]Zubair Nawaz, Ozana Silvia Dragomir, Thomas Marconi, Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems. FPT 2007: 301-304
Coauthor Index
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