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Journal Articles
- 2024
[j30]Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic. IEICE Trans. Inf. Syst. 107(12): 1476-1483 (2024)- 2023
- [j29]Morihiro Kuga, Qian Zhao, Yuya Nakazato, Motoki Amagasaki, Masahiro Iida:
An eFPGA Generation Suite with Customizable Architecture and IDE. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 560-574 (2023) - 2022
- [j28]Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Qian Zhao, Masahiro Iida:
Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 448-458 (2022) - [j27]Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida:
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks. IPSJ Trans. Syst. LSI Des. Methodol. 15: 16-19 (2022) - 2020
- [j26]Yasuhiro Nakahara, Masato Kiyama, Motoki Amagasaki, Masahiro Iida:
Relationship between Recognition Accuracy and Numerical Precision in Convolutional Neural Network Models. IEICE Trans. Inf. Syst. 103-D(12): 2528-2529 (2020) - [j25]Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito:
R-GCN Based Function Inference for Gate-level Netlist. IPSJ Trans. Syst. LSI Des. Methodol. 13: 69-71 (2020) - 2019
- [j24]Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida:
A SLM-based overlay architecture for fine-grained virtual FPGA. IEICE Electron. Express 16(24): 20190610 (2019) - 2018
- [j23]Motoki Amagasaki, Masato Ikebe, Qian Zhao, Masahiro Iida, Toshinori Sueyoshi:
Three Dimensional FPGA Architecture with Fewer TSVs. IEICE Trans. Inf. Syst. 101-D(2): 278-287 (2018) - [j22]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. IEICE Trans. Inf. Syst. 101-D(2): 335-343 (2018) - [j21]Teruaki Kitasuka, Takayuki Matsuzaki, Masahiro Iida:
Order Adjustment Approach Using Cayley Graphs for the Order/Degree Problem. IEICE Trans. Inf. Syst. 101-D(12): 2908-2915 (2018) - 2017
- [j20]Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. 100-D(4): 633-644 (2017) - [j19]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. IPSJ Trans. Syst. LSI Des. Methodol. 10: 63-70 (2017) - 2016
- [j18]Motoki Amagasaki, Ryo Araki, Masahiro Iida, Toshinori Sueyoshi:
SLM: A Scalable Logic Module Architecture with Less Configuration Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2500-2506 (2016) - [j17]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A Study of Heterogeneous Computing Design Method based on Virtualization Technology. SIGARCH Comput. Archit. News 44(4): 86-91 (2016) - 2015
- [j16]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. IEICE Trans. Inf. Syst. 98-D(2): 252-261 (2015) - [j15]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. Inf. Media Technol. 10(3): 425-431 (2015) - [j14]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A 3D FPGA Architecture to Realize Simple Die Stacking. IPSJ Trans. Syst. LSI Des. Methodol. 8: 116-122 (2015) - 2013
- [j13]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. 96-D(8): 1602-1612 (2013) - [j12]Yuki Ogawa, Masahiro Iida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi:
A reconfigurable Java accelerator with software compatibility for embedded systems. SIGARCH Comput. Archit. News 41(5): 71-76 (2013) - 2012
- [j11]Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi:
COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Trans. Inf. Syst. 95-D(2): 294-302 (2012) - [j10]Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. 95-D(2): 303-313 (2012) - [j9]Yoshihiro Ichinomiya, Tsuyoshi Kimura, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2347-2356 (2012) - 2011
- [j8]Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. IEEE Embed. Syst. Lett. 3(3): 89-92 (2011) - [j7]Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi:
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. 94-C(4): 548-556 (2011) - [j6]Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Improving the Soft-error Tolerability of a Soft-core Processor on. J. Next Gener. Inf. Technol. 2(3): 35-48 (2011) - [j5]Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
Parallelization of the channel width search for FPGA routing. SIGARCH Comput. Archit. News 39(4): 82-85 (2011) - 2010
- [j4]Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. 4(1): 5:1-5:24 (2010) - 2008
- [j3]Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi:
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfigurable Comput. 2008: 180216:1-180216:14 (2008) - 2007
- [j2]Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi:
A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices. IEICE Trans. Inf. Syst. 90-D(12): 1986-1989 (2007) - 2002
- [j1]Toshinori Sueyoshi, Masahiro Iida:
Configurable and Reconfigurable Computing for Digital Signal Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(3): 591-599 (2002)
Conference and Workshop Papers
- 2024
- [c56]Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS 2024: 1-6 - 2022
- [c55]Morihiro Kuga, Masahiro Iida, Hideharu Amano:
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL 2022: 467 - [c54]Kaito Taguchi, Kouichi Sakurai, Masahiro Iida:
Towards the Design of Locally Differential Private Hardware System for Edge Computing. CANDAR 2022: 186-191 - 2021
- [c53]Yuya Nakazato, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga:
Automation of Domain-specific FPGA-IP Generation and Test. HEART 2021: 4:1-4:6 - [c52]Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida:
Automatic executable code generation for DNN accelerator ReNA. CANDAR (Workshops) 2021: 107-113 - 2020
- [c51]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida:
Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. CANDAR 2020: 235-241 - [c50]Qian Zhao, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida, Takaichi Yoshida:
A Microcode-based Control Unit for Deep Learning Processors. IPDPS Workshops 2020: 139-142 - [c49]Mery Diana
, Motoki Amagasaki, Masahiro Iida:
Image Search System Based on Feature Vectors of Convolutional Neural Network. TENCON 2020: 934-939 - 2019
- [c48]Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, Takaichi Yoshida:
A Resource Reduced Application-Specific FPGA Switch. ARC 2019: 58-67 - [c47]Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida:
A Quantized Neural Network Library for Proper Implementation of Hardware Emulation. CANDAR Workshops 2019: 136-140 - [c46]Theingi Myint, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Masato Kiyama:
A Novel SLM-Based Virtual FPGA Overlay Architecture. MCSoC 2019: 74-80 - [c45]Masato Kiyama, Motoki Amagasaki, Masahiro Iida:
Deep Learning Framework with Arbitrary Numerical Precision. MCSoC 2019: 81-86 - 2017
- [c44]Qian Zhao, Masahiro Iida, Toshinori Sueyoshi:
A Study of FPGA Virtualization and Accelerator Scheduling. ETCD@ASPLOS 2017: 3:1-3:4 - [c43]Qian Zhao, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. FPT 2017: 267-270 - [c42]Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
FPGA based ASIC Emulator with High Speed Optical Serial Links. HEART 2017: 18:1-18:6 - [c41]Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
High-level Synthesis based on Parallel Design Patterns using a Functional Language. HEART 2017: 23:1-23:6 - 2016
- [c40]Qian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
hCODE: An open-source platform for FPGA accelerators. FPT 2016: 205-208 - [c39]Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi:
An area compact soft error resident circuit for FPGA. ICICDT 2016: 1-4 - [c38]Teruaki Kitasuka, Masahiro Iida:
A heuristic method of generating diameter 3 graphs for order/degree problem (invited paper). NOCS 2016: 1-6 - [c37]Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi:
A novel soft error tolerant FPGA architecture. VLSI-SoC 2016: 1-6 - 2015
- [c36]Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Simple wafer stacking 3D-FPGA architecture. ICICDT 2015: 1-4 - [c35]Motoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Architecture exploration of 3D FPGA to minimize internal layer connection. VLSI-SoC 2015: 110-115 - 2014
- [c34]Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL 2014: 1-6 - [c33]Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Zyndroid: An Android platform for software/hardware coprocessing. FPT 2014: 272-275 - [c32]Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi:
A novel three-dimensional FPGA architecture with high-speed serial communication links. FPT 2014: 306-309 - [c31]Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Blokus Duo engine on a Zynq. FPT 2014: 374-377 - 2013
- [c30]Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA 2013: 271 - [c29]Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL 2013: 1-7 - [c28]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An automatic FPGA design and implementation framework. FPL 2013: 1-4 - [c27]Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
An FPGA design and implementation framework combined with commercial VLSI CADs. ReCoSoC 2013: 1-7 - [c26]Tetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Three-dimensional stacking FPGA architecture using face-to-face integration. VLSI-SoC 2013: 192-197 - 2012
- [c25]Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. FCCM 2012: 241 - [c24]Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Fault detection and avoidance of FPGA in various granularities. FPL 2012: 539-542 - [c23]Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. FPT 2012: 220-223 - [c22]Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. ICA3PP (1) 2012: 139-152 - [c21]Makoto Fujino, Hiroki Tanaka, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. ICA3PP (1) 2012: 392-404 - [c20]Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A novel physical defects recovery technique for FPGA-IP cores. ReConFig 2012: 1-7 - [c19]Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC 2012: 225-230 - 2011
- [c18]Qian Zhao, Yusuke Iwai, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A novel reconfigurable logic device base on 3D stack technology. 3DIC 2011: 1-4 - [c17]Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Efficient Test Technique. FPL 2011: 291-294 - [c16]Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi:
An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109 - 2010
- [c15]Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM 2010: 47-54 - [c14]Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi:
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL 2010: 298-303 - [c13]Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL 2010: 304-309 - [c12]Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A robust reconfigurable logic device based on less configuration memory logic cell. FPT 2010: 162-169 - [c11]Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Power-aware FPGA routing fabrics and design tools. VLSI-SoC 2010: 67-72 - 2009
- [c10]Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC 2009: 97-109 - [c9]Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi:
Improvement of Execution Efficiency on the MX Core. PDCAT 2009: 420-425 - 2007
- [c8]Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi:
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC 2007: 142-154 - [c7]Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi:
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM 2007: 285-286 - [c6]Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi:
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM 2007: 309-310 - [c5]Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi:
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL 2007: 550-553 - [c4]Yoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi:
An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. FPT 2007: 241-244 - 2006
- [c3]Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi:
Effective clustering technique to optimize routability of outer cluster nets. FPGA 2006: 229 - [c2]Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi:
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC 2006: 198-203 - 2005
- [c1]Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi:
Applying the Small-World Network to Routing Structure of FPGAs. FPL 2005: 65-70
Parts in Books or Collections
- 2018
- [p2]Masahiro Iida:
What Is an FPGA? Principles and Structures of FPGAs 2018: 23-45 - [p1]Masahiro Iida:
Design Methodology. Principles and Structures of FPGAs 2018: 117-135
Informal and Other Publications
- 2021
- [i2]Masato Kiyama, Motoki Amagasaki, Masahiro Iida:
Development of Quantized DNN Library for Exact Hardware Emulation. CoRR abs/2106.08892 (2021) - 2016
- [i1]Teruaki Kitasuka, Masahiro Iida:
A Heuristic Method of Generating Diameter 3 Graphs for Order/Degree Problem. CoRR abs/1609.03136 (2016)
Coauthor Index
[j29] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [c53] [c52] [c51] [c50] [c49] [c47] [c46] [c45] [c43] [c42] [c41] [c40] [c39] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c8] [c5] [c4] [c2] [i2]
[j23] [j22] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c44] [c43] [c42] [c41] [c40] [c39] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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