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ORCID27th COOL CHIPS 2024: Tokyo, Japan
- IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2024, Tokyo, Japan, April 17-19, 2024. IEEE 2024, ISBN 979-8-3503-8414-7
- Muhammad Sulthan Mazaya, Eko Mursito Budi, Infall Syafalni, Nana Sutisna, Trio Adiono:
Reinforcement Learning Hardware Accelerator using Cache-Based Memoization for Optimized Q-Table Selection. 1-6 - Jueun Jung, Seungbin Kim, Bokyoung Seo, Wuyoung Jang, Sangho Lee, Jeongmin Shin, Donghyeon Han, Kyuho Jason Lee
:
A Low-power and Real-time Semantic LiDAR SLAM Processor with Point Neural Network Segmentation and kNN Acceleration for Mobile Robots. 1-3 - Seunghyun Park, Daejin Park:
Bit-Separable Radix-4 Booth Multiplier for Power-Efficient CNN Accelerator. 1-6 - Qi Li, Masato Edahiro:
Template-Based Automatic Library Function Generation with Halide for Compute-Intensive Simulink Models. 1-6 - Junha Ryu, Hankyul Kwon, Wonhoon Park, Zhiyong Li, Beomseok Kwon, Donghyeon Han, Dongseok Im, Sangyeob Kim, Hyungnam Joo, Minsung Kim, Hoi-Jun Yoo:
A Low-Power Neural Graphics System for Instant 3D Modeling and Real-Time Rendering on Mobile AR/VR Devices. 1-3 - Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
Branch Divergence-Aware Flexible Approximating Technique on GPUs. 1-6 - Zirui Lin, Katsutoshi Itoyama, Kazuhiro Nakadai, Hideharu Amano:
FPGA-based Low Power Acceleration of HARK Sound Source Localization. 1-6 - Dohyun Kim, Koki Asahina, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays. 1-5 - Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Sangyeob Kim, Hoi-Jun Yoo:
NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator. 1-3 - Gwangtae Park, Seokchan Song, Haoyang Sang, Dongseok Im, Donghyeon Han, Sangyeob Kim, Hongseok Lee, Hoi-Jun Yoo:
A Low-power and Real-time Neural-Rendering Dense SLAM Processor with 3-Level Hierarchical Sparsity Exploitation. 1-3 - Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima:
MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. 1-6 - Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. 1-6 - Kento Mishima, Naoya Niwa, Kazutoshi Wakabayashi, Hiroe Iwasaki:
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions. 1-3 - Simon Friedrich, Robert Wittig, Emil Matús, Darius Grantz, Martin Zeller, Jens Benndorf, Gerhard P. Fettweis:
A 22 nm 10 TOPS Mixed-Precision Neural Network SoC for Image Processing with Energy-Efficient Dilated Convolution Support. 1-3 - Daiki Saito, Siyi Hu, Yukinori Sato:
A Microservice Scheduler for Heterogeneous Resources on Edge-Cloud Computing Continuum. 1-6
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