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Books and Theses
- 2008
[b1]Parag K. Lala:
An Introduction to Logic Circuit Testing. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2008, ISBN 978-3-031-79784-2
Journal Articles
- 2010
- [j26]Parag K. Lala, Adam Mathews, James Patrick Parkerson:
An Approach for Implementing State Machines with Online Testability. VLSI Design 2010: 639747:1-639747:7 (2010) - 2007
- [j25]Jia Di, Parag K. Lala:
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. J. Electron. Test. 23(2-3): 175-192 (2007) - [j24]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12): 2696-2705 (2007) - 2006
- [j23]Parag K. Lala, B. Kiran Kumar, James Patrick Parkerson:
On self-healing digital system design. Microelectron. J. 37(4): 353-362 (2006) - [j22]Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson:
Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. 55(2): 406-414 (2006) - 2003
- [j21]Parag K. Lala, B. Kiran Kumar:
An Architecture for Self-Healing Digital Systems. J. Electron. Test. 19(5): 523-535 (2003) - [j20]Parag K. Lala, Alfred L. Burress:
Self-checking logic design for FPGA implementation. IEEE Trans. Instrum. Meas. 52(5): 1391-1398 (2003) - 2001
- [j19]Parag K. Lala, Alvernon Walker:
A Fine Grain Configurable Logic Block for Self-checking FPGAs. VLSI Design 12(4): 527-536 (2001) - 2000
- [j18]Parag K. Lala:
Guest Editorial. VLSI Design 11(1) (2000) - 1998
- [j17]Parag K. Lala:
Guest Editorial. VLSI Design 5(4) (1998) - [j16]Fadi Busaba, Parag K. Lala, Alvernon Walker:
On Self-Checking Design of CMOS Circuits for Multiple Faults. VLSI Design 7(2): 151-161 (1998) - 1996
- [j15]D. A. Pierce, Parag K. Lala:
Modular implementation of efficient self-checking checkers for the Berger code. J. Electron. Test. 9(3): 279-294 (1996) - [j14]K. Lai, Parag K. Lala:
Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set. IEEE Trans. Computers 45(6): 763-765 (1996) - 1994
- [j13]Fadi Y. Busaba, Parag K. Lala:
Self-checking combinational circuit design for single and unidirectional multibit error. J. Electron. Test. 5(1): 19-28 (1994) - [j12]J. Q. Wang, Parag K. Lala:
Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker. IEEE Trans. Computers 43(10): 1238-1240 (1994) - [j11]Fadi Busaba, Parag K. Lala:
An Approach for Self-Checking Realization of Interacting Finite State Machines. VLSI Design 1(4): 335-343 (1994) - [j10]Fadi Busaba, Parag K. Lala:
Techniques for Self-Checking Combinational Logic Synthesis. VLSI Design 2(3): 209-221 (1994) - 1992
- [j9]Alvernon Walker, Winser E. Alexander, Parag K. Lala:
Fault Diagnosis in Analog Circuits Using Element Modulation. IEEE Des. Test Comput. 9(1): 19-29 (1992) - [j8]Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala:
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. IEEE Trans. Computers 41(7): 881-886 (1992) - 1991
- [j7]Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala:
A Note on t-EC/d-UED Codes. IEEE Trans. Computers 40(5): 660-663 (1991) - 1990
- [j6]Parag K. Lala:
A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips. Microprocessing and Microprogramming 29(4): 217-223 (1990) - 1988
- [j5]Dali L. Tao, Parag K. Lala, Carlos R. P. Hartmann:
A MOS implementation of totally self-checking checker for the 1-out-of-3 code. IEEE J. Solid State Circuits 23(3): 875-877 (1988) - [j4]Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala:
An efficient class of unidirectional error detecting/correcting codes. IEEE Trans. Computers 37(6): 879-882 (1988) - 1985
- [j3]Parag K. Lala:
Fault tolerance and self-checking techniques in microprocessor-based system design. Softw. Microsystems 4(3): 50-52 (1985) - 1984
- [j2]Nigel F. Scholes, Gary Morgan, Parag K. Lala:
Redefinable crossassembler for horizontally microprogrammable processors. Microprocess. Microsystems 8(4): 177-181 (1984) - 1981
- [j1]Parag K. Lala:
Testing using a minimal number of instructions. Microprocess. Microsystems 5(7): 295-298 (1981)
Conference and Workshop Papers
- 2010
- [c39]Parag K. Lala:
A Quantum Key Distribution Protocol. Security and Management 2010: 225-228 - 2008
- [c38]Parag K. Lala:
On FPGA Design with Self-checking and Fault Tolerance Capability. ERSA 2008: 29-34 - 2005
- [c37]Dilip P. Vasudevan, Parag K. Lala:
A Technique for Modular Design of Self-Checking Carry-Select Adder. DFT 2005: 325-333 - [c36]Jia Di, Parag K. Lala, Dilip P. Vasudevan:
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT 2005: 371-379 - [c35]C. K. Tang, Parag K. Lala, James Patrick Parkerson:
A Technique for Designing Totally Self-Checking Domino Logic Circuits. ISQED 2005: 128-132 - [c34]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI 2005: 309-310 - 2004
- [c33]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium 2004: 325-330 - [c32]Dilip P. Vasudevan, Parag K. Lala:
A New Reversible Logic Gate and its Applications. ESA/VLSI 2004: 480-484 - [c31]Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT 2004: 324-331 - [c30]Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala:
Logic implementation using a reversible gate. Circuits, Signals, and Systems 2004: 452-456 - 2003
- [c29]Parag K. Lala:
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. DFT 2003: 235-241 - [c28]Parag K. Lala, B. Kiran Kumar:
An FPGA architecture with built-in error correction capability. FPGA 2003: 245 - [c27]Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala:
On-Line Error Detecting Constant Delay Adder. IOLTS 2003: 17- - [c26]S. R. Seward, Parag K. Lala:
Fault Injection in Digital Logic Circuits at the VHDL Level. IOLTS 2003: 161 - [c25]S. R. Seward, Parag K. Lala:
Fault Injection for Verifying Testability at the VHDL Level. ITC 2003: 131-137 - [c24]B. Kiran Kumar, Parag K. Lala:
On-line Detection of Faults in Carry-Select Adders. ITC 2003: 912-918 - 2002
- [c23]Parag K. Lala, K. K. Bondali:
On Biologically-Inspired Design of Fault-Tolerant Digital Systems. DELTA 2002: 287-290 - [c22]Parag K. Lala, B. Kiran Kumar:
An Architecture for Self-Healing Digital Systems. IOLTW 2002: 3-7 - [c21]Parag K. Lala, B. Kiran Kumar:
Human Immune System Inspired Architecture for Self-Healing Digital Systems. ISQED 2002: 292-297 - [c20]Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala:
On-line Error Detection in a Carry-free Adder. IWLS 2002: 251-254 - 2001
- [c19]Parag K. Lala, Alvernon Walker:
A Unified Scheme for Designing Testable State Machines. Asian Test Symposium 2001: 273-278 - [c18]Parag K. Lala, Alvernon Walker:
On-Line Error Detectable Carry-Free Adder Design. DFT 2001: 66-71 - [c17]Parag K. Lala, Mark G. Karpovsky:
An Approach for Designing On-Line Testable State Machines. IOLTW 2001: 135 - 2000
- [c16]Parag K. Lala, Alvernon Walker:
An On-Line Reconfigurable FPGA Architecture. DFT 2000: 275- - [c15]Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim:
Fault Analysis of the Multiple Valued Logic Using Spectral Method. ISMVL 2000: 59-66 - [c14]Alvernon Walker, Parag K. Lala:
A Transition Based BIST Approach for Passive Analog Circuits. ISQED 2000: 347-354 - 1999
- [c13]Parag K. Lala, Anup Singh, Alvernon Walker:
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. DFT 1999: 238-246 - [c12]Parag K. Lala, Alfred L. Burress:
Self-Checking Logic Design for LUT-Based FPGAs. FPGA 1999: 253 - [c11]Parag K. Lala, Alfred L. Burress:
A technique for designing self-checking logic for FPGAs. ISCAS (1) 1999: 94-96 - 1997
- [c10]Alvernon Walker, Algernon P. Henry, Parag K. Lala:
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. DFT 1997: 272-280 - [c9]Alfred L. Burress, Parag K. Lala:
On-Line Testable Logic Desgin for FPGA Implementation. ITC 1997: 471-478 - 1996
- [c8]Parag K. Lala, S. Yang, Fadi Busaba:
A unified approach for off-line and on-line testing of VLSI systems. DFT 1996: 195-203 - 1995
- [c7]Fadi Y. Busaba, Parag K. Lala:
A graph coloring based approach for self-checking logic circuit design. Asian Test Symposium 1995: 327- - 1993
- [c6]Fadi Y. Busaba, Parag K. Lala:
Input and output encoding techniques for on-line error detection in combinational logic circuits. VTS 1993: 48-54 - 1992
- [c5]Manjit S. Cheema, Parag K. Lala:
A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. VTS 1992: 155-159 - [c4]B. Kolla, Parag K. Lala, K. C. Yarlagadda:
A concurrent checking scheme for single and multibit errors in logic circuits. VTS 1992: 160-164 - 1991
- [c3]Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda:
An approach for designing self-checking logic using residue codes. VTS 1991: 166-171 - 1986
- [c2]Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala:
A Concurrent Testing Strategy for PLAs. ITC 1986: 705-709 - [c1]Parag K. Lala:
On Built-In Testing of VLSI Chips. ITC 1986: 719-721
Coauthor Index
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