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ORCIDJavier Valls-Coquillat
Javier Valls
Person information
- affiliation: Polytechnic University of Valencia, Spain
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2020 – today
- 2024
[j47]Gerardo José Ginovart-Panisello
, Ignasi Iriondo, Tesa Panisello Monjo, Silvia Riva, Rodrigo Garcia, Javier Valls, Rosa Maria Alsina Pages:
Acoustic detection of the effects of prolonged fasting on newly hatched broiler chickens. Comput. Electron. Agric. 219: 108763 (2024)- 2023
- [j46]Pau Salvador, Vicenç Almenar, Juan Luis Corral, Javier Valls, María José Canet:
Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links. Sensors 23(10): 4637 (2023) - [c38]Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls:
Layered Decoding of Quantum LDPC Codes. ISTC 2023: 1-5 - 2021
- [j45]Javier Valls, Francisco Garcia-Herrero, Nithin Raveendran, Bane Vasic:
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes. IEEE Access 9: 138734-138743 (2021)
2010 – 2019
- 2019
- [j44]Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Garcia-Herrero:
Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems. Circuits Syst. Signal Process. 38(4): 1793-1810 (2019) - [j43]J. M. Català-Pérez, Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls, David Declercq:
Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. Circuits Syst. Signal Process. 38(11): 5068-5080 (2019) - [j42]Julián S. Bruno, Vicenç Almenar, Javier Valls:
FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems. Microprocess. Microsystems 64: 195-204 (2019) - [j41]Javier Valls, Vicente Torres, María José Canet, Francisco Miguel Garcia-Herrero:
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2198-2207 (2019) - 2018
- [c37]Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Miguel Garcia-Herrero:
High-Throughput One-Channel RS(255, 239) Decoder. DSD 2018: 110-114 - [c36]Roberto Llorente, Maria Morant, Julián S. Bruno, Vicenç Almenar, Juan Luis Corral, Jose M. Fuster, Javier Valls:
Multidimensional Multiplexing in Multicore Fibre for Hybrid Optical Backhaul provision: The XCORE Approach. ICTON 2018: 1-4 - [c35]Vicente Torres, Javier Valls, María José Canet, Francisco Garcia-Herrero:
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239). NEWCAS 2018: 305-308 - 2017
- [j40]Vicente Torres, Javier Valls, Richard G. Lyons:
Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks]. IEEE Signal Process. Mag. 34(6): 164-169 (2017) - [j39]Vicente Torres, Javier Valls:
A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2663-2667 (2017) - 2016
- [j38]Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls:
High-Performance NB-LDPC Decoder With Reduction of Message Exchange. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1950-1961 (2016) - [j37]Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls:
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2643-2653 (2016) - 2015
- [j36]Julián S. Bruno, Vicenç Almenar, Javier Valls, Juan L. Corral:
Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser. JOCN 7(11): 1025-1033 (2015) - [j35]Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls-Coquillat, David Declercq:
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(1): 177-184 (2015) - [j34]Jesus Omar Lacruz, Francisco Garcia-Herrero, David Declercq, Javier Valls:
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1783-1792 (2015) - [j33]Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls:
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2676-2679 (2015) - [c34]Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma José Canet, Javier Valls, Asuncion Perez-Pascual:
A 630 Mbps non-binary LDPC decoder for FPGA. ISCAS 2015: 1989-1992 - 2014
- [j32]Francisco Garcia-Herrero, David Declercq, Javier Valls:
Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes. IEEE Commun. Lett. 18(5): 749-752 (2014) - [j31]J. M. Català-Pérez, Francisco Garcia-Herrero, Javier Valls, K. Liu, Shu Lin:
Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree. IEEE Commun. Lett. 18(12): 2065-2068 (2014) - [j30]Guillermo A. Jaquenod, Javier Valls, Javier Siman:
Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain. Int. J. Reconfigurable Comput. 2014: 546264:1-546264:5 (2014) - [j29]Fabian Angarita, Javier Valls, Vicenç Almenar, Vicente Torres-Carot:
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2150-2158 (2014) - [j28]Francisco Garcia-Herrero, María José Canet, Javier Valls:
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1455-1459 (2014) - [j27]Francisco Garcia-Herrero, Erbao Li, David Declercq, Javier Valls:
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2256-2267 (2014) - [c33]Francisco Garcia-Herrero, David Declercq, Javier Valls:
A symbol flipping decoder for NB-LDPC relying on multiple votes. ISTC 2014: 203-207 - 2013
- [j26]Francisco Garcia-Herrero, María José Canet, Javier Valls:
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes. Circuits Syst. Signal Process. 32(2): 727-741 (2013) - [c32]Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls:
Low latency T-EMS decoder for non-binary LDPC codes. ACSSC 2013: 831-835 - [c31]Francisco Garcia-Herrero, Ma José Canet, Javier Valls:
High-speed NB-LDPC decoder for wireless applications. ISPACS 2013: 215-220 - 2012
- [j25]Francisco Garcia-Herrero, María José Canet, Javier Valls, Mark F. Flanagan:
Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes. IEEE Commun. Lett. 16(6): 909-912 (2012) - [j24]Fabian Angarita, José Marín-Roig, Vicenç Almenar, Javier Valls:
Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation. IET Commun. 6(16): 2575-2581 (2012) - [j23]María José Canet, Javier Valls, Vicenç Almenar, José Marín-Roig:
FPGA implementation of an OFDM-based WLAN receiver. Microprocess. Microsystems 36(3): 232-244 (2012) - [j22]Roberto Gutiérrez, Vicente Torres-Carot, Javier Valls:
Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method. IEEE Trans. Circuits Syst. II Express Briefs 59-II(8): 501-505 (2012) - [j21]Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher:
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 568-573 (2012) - [j20]Fabian Angarita, Trinidad Sansaloni, María José Canet, Javier Valls:
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 66(2): 99-104 (2012) - [j19]Fabian Angarita, Trinidad Sansaloni, Asuncion Perez-Pascual, Javier Valls:
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 68(2): 139-149 (2012) - [j18]María José Canet, Vicenc Almenar-Terre, Santiago J. Flores, Javier Valls:
Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. J. Signal Process. Syst. 68(3): 287-301 (2012) - [c30]Fabian Angarita, Vicente Torres-Carot, Asuncion Perez-Pascual, Javier Valls:
High-throughput FPGA-based emulator for structured LDPC codes. ICECS 2012: 404-407 - [c29]Vicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls:
Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. ICECS 2012: 408-411 - [c28]Francisco Garcia-Herrero, María José Canet, Javier Valls:
Decoder for an enhanced serial generalized bit flipping algorithm. ICECS 2012: 412-415 - 2011
- [j17]Francisco Garcia-Herrero, Javier Valls, Pramod Kumar Meher:
High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits Syst. Signal Process. 30(6): 1643-1669 (2011) - [j16]Roberto Gutiérrez, Javier Valls:
Low Cost Hardware Implementation of Logarithm Approximation. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2326-2330 (2011) - 2010
- [j15]Roberto Gutiérrez, Vicente Torres-Carot, Javier Valls-Coquillat:
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques. J. Syst. Archit. 56(11): 588-596 (2010)
2000 – 2009
- 2009
- [j14]Fabian Angarita, Ma José Canet, Trinidad Sansaloni, Vicenç Almenar, Javier Valls:
Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN. J. Circuits Syst. Comput. 18(7): 1333-1337 (2009) - [j13]Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna:
50 Years of CORDIC: Algorithms, Architectures, and Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1893-1907 (2009) - [j12]Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J. Signal Process. Syst. 56(1): 17-23 (2009) - [j11]Roberto Gutiérrez, Javier Valls:
Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications. J. Signal Process. Syst. 56(1): 25-33 (2009) - [j10]A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre, Javier Valls:
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. J. Signal Process. Syst. 56(1): 35-40 (2009) - [c27]Roberto Gutiérrez, Javier Valls, Asuncion Perez-Pascual:
FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. FPL 2009: 609-612 - 2008
- [j9]Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre:
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder. J. Signal Process. Syst. 52(1): 35-44 (2008) - [j8]Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls:
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. J. Signal Process. Syst. 52(2): 181-191 (2008) - [c26]José Marín-Roig, Vicenç Almenar, Javier Valls, Ma José Canet:
64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm. ICECS 2008: 610-613 - 2007
- [j7]Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres-Carot, Vicenç Almenar, José F. Toledo, Javier Valls:
FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. IEEE Trans. Educ. 50(3): 229-235 (2007) - [j6]T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls:
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J. VLSI Signal Process. 47(2): 183-187 (2007) - [c25]A. Perez-Pascual, T. Sansaloni, Vicente Torres, Vicenç Almenar, Javier Valls:
Design of an efficient digital down-converter for a SDR-based DVB-S receiver. ECCTD 2007: 256-259 - [c24]Ma José Canet, Vicenç Almenar, Santiago J. Flores, Javier Valls:
Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard. EUSIPCO 2007: 560-564 - [c23]Roberto Gutiérrez, Javier Valls:
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms. FPL 2007: 472-475 - [c22]Fabian Angarita Preciado, María José Canet, Trinidad Sansaloni Balaguer, Vicenc Almenar-Terre, Javier Valls-Coquillat:
Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN. ICECS 2007: 586-588 - [c21]María José Canet, Vicenç Almenar, José Marín-Roig, Javier Valls:
Time Synchronization for the IEEE 802.11a/g WLAN Standard. PIMRC 2007: 1-5 - 2006
- [j5]Javier Valls, Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres, Vicenç Almenar:
The use of CORDIC in software defined radios: a tutorial. IEEE Commun. Mag. 44(9): 46-50 (2006) - [c20]Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Design of high performance timing recovery loops for communication applications. SiPS 2006: 1-4 - 2005
- [c19]Ma José Canet, Ian J. Wassell, Javier Valls, Vicenç Almenar:
Performance evaluation of fine time synchronizers for WLANs. EUSIPCO 2005: 1-4 - [c18]Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo:
Statistical Power Estimation for FPGA. FPL 2005: 515-518 - [c17]Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. FPL 2005: 535-538 - 2004
- [c16]Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls:
Power analysis and estimation tool integrated with XPOWER. FPGA 2004: 259 - [c15]Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima:
Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. FPL 2004: 494-504 - [c14]Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima:
A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. PIMRC 2004: 531-535 - 2003
- [j4]Francisco Cardells-Tormo, Javier Valls-Coquillat:
Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 50(3): 135-138 (2003) - [j3]Javier Valls, Eduardo I. Boemo:
Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 317-322 (2003) - [j2]T. Sansaloni, Javier Valls, Keshab K. Parhi:
Digit-Serial Complex-Number Multipliers on FPGAs. J. VLSI Signal Process. 33(1-2): 105-115 (2003) - [c13]Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre:
Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S. FPL 2003: 31-40 - [c12]José Marín-Roig, Vicente Torres-Carot, Ma José Canet, Asuncion Perez-Pascual, Trinidad Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat:
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. FPL 2003: 988-991 - [c11]Francisco Cardells-Tormo, Javier Valls-Coquillat:
Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs. ISCAS (2) 2003: 260-263 - 2002
- [j1]Javier Valls, Martin Kuhlmann, Keshab K. Parhi:
Evaluation of CORDIC Algorithms for FPGA Design. J. VLSI Signal Process. 32(3): 207-222 (2002) - [c10]Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-Carot:
Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard. FPL 2002: 102-111 - [c9]Francisco Cardells-Tormo, Javier Valls-Coquillat:
High Performance Quadrature Digital Mixers for FPGAs. FPL 2002: 905-914 - [c8]A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA-based radix-4 butterflies for HIPERLAN/2. ISCAS (3) 2002: 277-280 - 2001
- [c7]T. Sansaloni, A. Perez-Pascual, Javier Valls:
Distributed arithmetic radix-2 butterflies for FPGA. ICECS 2001: 521-524 - [c6]A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA based on-line complex-number multipliers. ICECS 2001: 1481-1484 - 2000
- [c5]Trinidad Sansaloni, Javier Valls, Keshab K. Parhi:
FPGA-based digit-serial complex number multiplier-accumulator. ISCAS 2000: 585-588
1990 – 1999
- 1999
- [c4]Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo:
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. ICECS 1999: 241-244 - [c3]A. Perez-Pascual, Javier Valls, Marcos M. Peiró:
Efficient complex-number multipliers mapped on FPGA. ICECS 1999: 1123-1126 - [c2]Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo:
Fast FPGA-based pipelined digit-serial/parallel multipliers. ISCAS (1) 1999: 482-485 - 1998
- [c1]Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo:
Design and FPGA implementation of digit-serial FIR filters. ICECS 1998: 191-194
Coauthor Index
Vicenc Almenar-Terre
aka: Vicenç Almenar
aka: Vicenç Almenar
Fabian Angarita
aka: Fabian Angarita Preciado
aka: Fabian Angarita Preciado
Ma José Canet
aka: María José Canet
aka: María José Canet
Francisco Garcia-Herrero
aka: Francisco Miguel Garcia-Herrero
aka: Francisco Miguel Garcia-Herrero
Asuncion Perez-Pascual
aka: A. Perez-Pascual
aka: A. Perez-Pascual
Vicente Torres 0001
aka: Vicente Torres-Carot
aka: Vicente Torres-Carot
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