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"A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE ..."

Ma José Canet et al. (2004)

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DOI: 10.1109/PIMRC.2004.1370927

access: closed

type: Conference or Workshop Paper

metadata version: 2017-07-12

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Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima:
A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems. PIMRC 2004: 531-535

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