"Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2."

Ma José Canet et al. (2004)

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DOI: 10.1007/978-3-540-30117-2_51

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima:
Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. FPL 2004: 494-504

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