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2020 – today
- 2024
[c15]P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne:
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. VLSI Technology and Circuits 2024: 1-2- 2023
- [c14]Eric Beyne, Anne Jourdain, Gerald Beyer:
Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). VLSI Technology and Circuits 2023: 1-2 - [c13]Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou
, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c12]Anabela Veloso, Geert Eneman, An De Keersgieter, P. Favia, Andriy Hikavyy, Rongmei Chen, Anne Jourdain, N. Horiguchi:
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. ICICDT 2022: 51-54 - [c11]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c10]A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi:
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits 2022: 330-331 - [c9]Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne:
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - [c8]Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi:
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits 2022: 431-432
2010 – 2019
- 2016
- [c7]Jaber Derakhshandeh, Lin Hou, Inge De Preter, Carine Gerets, Samuel Suhard, Vikas Dubey, Geraldine Jamieson, Fumihiro Inoue, Tomas Webers, Pieter Bex, Giovanni Capuz, Eric Beyne, John Slabbekoorn, Teng Wang, Anne Jourdain, Gerald Beyer, Kenneth June Rebibis, Andy Miller:
Die to wafer 3D stacking for below 10um pitch microbumps. 3DIC 2016: 1-4 - [c6]Anne Jourdain, Joeri De Vos, Fumihiro Inoue, Kenneth J. Rebibis, Andy Miller, Gerald Beyer, Eric Beyne, Edward Walsby, Jash Patel, Oliver Ansell, Janet Hopkins, Huma Ashraf, Dave Thomas:
Extreme wafer thinning optimization for via-last applications. 3DIC 2016: 1-5 - 2012
- [j2]Harrie A. C. Tilmans, Jeroen De Coster, Philippe Hélin, Vladimir Cherman, Anne Jourdain, Piet De Moor, Bart Vandevelde, Nga P. Pham, Joseph Zekry, Ann Witvrouw, Ingrid De Wolf:
MEMS packaging and reliability: An undividable couple. Microelectron. Reliab. 52(9-10): 2228-2234 (2012) - 2011
- [c5]Y. H. Hu, C. S. Liu, M. J. Lii, Kenneth J. Rebibis, Anne Jourdain, Antonio La Manna, Gerald Beyer, Eric Beyne, C. H. Yu:
3D stacking using Cu-Cu direct bonding. 3DIC 2011: 1-4 - [c4]Alain Phommahaxay, Anne Jourdain, Greet Verbinnen, Tobias Woitke, Peter Bisson, Markus Gabriel, Walter Spiess, Alice Guerrero, Jeremy McCutcheon, Rama Puligadda, Pieter Bex, Axel Van den Eede, Bart Swinnen, Gerald Beyer, Andy Miller, Eric Beyne:
Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. 3DIC 2011: 1-4 - 2010
- [c3]Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne, Youssef Travaly, Bart Swinnen:
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. 3DIC 2010: 1-4
2000 – 2009
- 2009
- [c2]Ramakanth Alapati, Youssef Travaly, Jan Van Olmen, Ricardo Cotrin Teixeira, Jan Vaes, Marc van Cauwenbergh, Anne Jourdain, Greet Verbinnen, Gino Marcuccilli, Glenn Florence, Shay Wolfling, Christine Pelissier, Haiping Zhang, Jaydeep Sinha, Andreas Machura, Irfan Malik:
TSV metrology and inspection challenges. 3DIC 2009: 1-4 - [c1]Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen:
3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). 3DIC 2009: 1-5 - 2004
- [j1]Robert Modlinski, Ann Witvrouw, Petar Ratchev, Anne Jourdain, Veerle Simons, H. A. C. Tilmans, Jaap M. J. den Toonder, Robert Puers, Ingrid De Wolf:
Creep as a reliability problem in MEMS. Microelectron. Reliab. 44(9-11): 1733-1738 (2004)
Coauthor Index
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