"Backside Power Delivery with relaxed overlay for backside patterning using ..."

P. Zhao et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631441

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-23

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P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne:
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. VLSI Technology and Circuits 2024: 1-2

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