"Block-level Evaluation and Optimization of Backside PDN for ..."

Giuliano Sisto et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185211

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-20

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Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2

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